From 00a84d0eddec8e671f48e209fffac7c97e6bc4bf Mon Sep 17 00:00:00 2001
From: Sheldon Lobo <sheldon.lobo@oracle.com>
Date: Thu, 18 May 2017 09:34:26 +0000
Subject: [PATCH] Minor SPARC T4 and M7 fixes and additions.
* config/sparc/sparc.c (sparc_option_override): Set function
alignment for -mcpu=niagara7 to 64 to match the I$ line.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC M7 branch
latency to 1.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC T4 branch
latency to 2.
* config/sparc/sol2.h: Fix a ASM_CPU32_DEFAULT_SPEC typo.
* gcc.target/sparc/niagara7-align.c: New test.
From-SVN: r248184
---
gcc/ChangeLog | 10 ++++++++++
gcc/config/sparc/sol2.h | 2 +-
gcc/config/sparc/sparc.c | 13 ++++++++-----
gcc/config/sparc/sparc.h | 11 +++++++++--
gcc/testsuite/ChangeLog | 4 ++++
gcc/testsuite/gcc.target/sparc/niagara7-align.c | 4 ++++
6 files changed, 36 insertions(+), 8 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/sparc/niagara7-align.c
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f839cb0600f8..a9978bca0164 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2017-05-18 Sheldon Lobo <sheldon.lobo@oracle.com>
+
+ * config/sparc/sparc.c (sparc_option_override): Set function
+ alignment for -mcpu=niagara7 to 64 to match the I$ line.
+ * config/sparc/sparc.h (BRANCH_COST): Set the SPARC M7 branch
+ latency to 1.
+ * config/sparc/sparc.h (BRANCH_COST): Set the SPARC T4 branch
+ latency to 2.
+ * config/sparc/sol2.h: Fix a ASM_CPU32_DEFAULT_SPEC typo.
+
2017-05-18 Marek Polacek <polacek@redhat.com>
PR sanitizer/80797
diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h
index db24ca3fc3fb..8a50bfeefc7f 100644
--- a/gcc/config/sparc/sol2.h
+++ b/gcc/config/sparc/sol2.h
@@ -169,7 +169,7 @@ along with GCC; see the file COPYING3. If not see
#undef CPP_CPU64_DEFAULT_SPEC
#define CPP_CPU64_DEFAULT_SPEC ""
#undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAUILT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG
+#define ASM_CPU32_DEFAULT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG
#undef ASM_CPU64_DEFAULT_SPEC
#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA7_FLAG
#endif
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 8277496964ac..6dfb2698c71e 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1528,15 +1528,18 @@ sparc_option_override (void)
target_flags |= MASK_LRA;
/* Supply a default value for align_functions. */
- if (align_functions == 0
- && (sparc_cpu == PROCESSOR_ULTRASPARC
+ if (align_functions == 0)
+ {
+ if (sparc_cpu == PROCESSOR_ULTRASPARC
|| sparc_cpu == PROCESSOR_ULTRASPARC3
|| sparc_cpu == PROCESSOR_NIAGARA
|| sparc_cpu == PROCESSOR_NIAGARA2
|| sparc_cpu == PROCESSOR_NIAGARA3
- || sparc_cpu == PROCESSOR_NIAGARA4
- || sparc_cpu == PROCESSOR_NIAGARA7))
- align_functions = 32;
+ || sparc_cpu == PROCESSOR_NIAGARA4)
+ align_functions = 32;
+ else if (sparc_cpu == PROCESSOR_NIAGARA7)
+ align_functions = 64;
+ }
/* Validate PCC_STRUCT_RETURN. */
if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 590a5f4dbf39..686a3d521939 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1566,7 +1566,10 @@ do { \
and annulled branches insert 4 bubbles.
On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas
- a taken branch costs 6 cycles. */
+ a taken branch costs 6 cycles.
+
+ The T4 Supplement specifies the branch latency at 2 cycles.
+ The M7 Supplement specifies the branch latency at 1 cycle. */
#define BRANCH_COST(speed_p, predictable_p) \
((sparc_cpu == PROCESSOR_V9 \
@@ -1579,7 +1582,11 @@ do { \
: ((sparc_cpu == PROCESSOR_NIAGARA2 \
|| sparc_cpu == PROCESSOR_NIAGARA3) \
? 5 \
- : 3))))
+ : (sparc_cpu == PROCESSOR_NIAGARA4 \
+ ? 2 \
+ : (sparc_cpu == PROCESSOR_NIAGARA7 \
+ ? 1 \
+ : 3))))))
/* Control the assembler format that we output. */
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d5ea15c9bcef..fca9165d0ce5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2017-05-18 Sheldon Lobo <sheldon.lobo@oracle.com>
+
+ * gcc.target/sparc/niagara7-align.c: New test.
+
2017-05-18 Marek Polacek <polacek@redhat.com>
PR sanitizer/80797
diff --git a/gcc/testsuite/gcc.target/sparc/niagara7-align.c b/gcc/testsuite/gcc.target/sparc/niagara7-align.c
new file mode 100644
index 000000000000..a46aac17c329
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/niagara7-align.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-falign-functions -mcpu=niagara7" } */
+/* { dg-final { scan-assembler "\.align 64" } } */
+void foo(void) {}
--
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