From 01f50ebfd97a7bd17a4cc94c403a8e126986c02c Mon Sep 17 00:00:00 2001
From: Jeff Law <jlaw@ventanamicro.com>
Date: Sun, 20 Oct 2024 10:35:18 -0600
Subject: [PATCH] Revert "[PATCH 7/7] RISC-V: Disable by pieces for vector
setmem length > UNITS_PER_WORD"
This reverts commit 72ceddbfb78dbb95f0808c3eca1765e8cd48b023.
---
gcc/config/riscv/riscv.cc | 19 -------------------
.../gcc.target/riscv/rvv/autovec/pr113469.c | 3 +--
.../gcc.target/riscv/rvv/base/setmem-2.c | 12 +++++-------
.../gcc.target/riscv/rvv/base/setmem-3.c | 12 +++++-------
4 files changed, 11 insertions(+), 35 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index fc2a83b21876..3ac40234345a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -12583,22 +12583,6 @@ riscv_stack_clash_protection_alloca_probe_range (void)
return STACK_CLASH_CALLER_GUARD;
}
-static bool
-riscv_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
- unsigned alignment,
- enum by_pieces_operation op, bool speed_p)
-{
- /* For set/clear with size > UNITS_PER_WORD, by pieces uses vector broadcasts
- with UNITS_PER_WORD size pieces. Use setmem<mode> instead which can use
- bigger chunks. */
- if (TARGET_VECTOR && stringop_strategy & STRATEGY_VECTOR
- && (op == CLEAR_BY_PIECES || op == SET_BY_PIECES)
- && speed_p && size > UNITS_PER_WORD)
- return false;
-
- return default_use_by_pieces_infrastructure_p (size, alignment, op, speed_p);
-}
-
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -12964,9 +12948,6 @@ riscv_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
#undef TARGET_C_MODE_FOR_FLOATING_TYPE
#define TARGET_C_MODE_FOR_FLOATING_TYPE riscv_c_mode_for_floating_type
-#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
-#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P riscv_use_by_pieces_infrastructure_p
-
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113469.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113469.c
index f86084bdb40f..d1c118c02d6e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113469.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113469.c
@@ -51,5 +51,4 @@ void p(int buf, __builtin_va_list ab, int q) {
} while (k);
}
-/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*4,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*8,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*4,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
index 838fbebadff3..faea442a4bdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
@@ -5,17 +5,15 @@
#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
-/* Vectorise with no loop.
+/* Small memsets shouldn't be vectorised.
** f1:
** (
-** vsetivli\s+zero,\d+,e8,m1,ta,ma
+** sb\s+a1,0\(a0\)
+** ...
** |
-** li\s+a\d+,\d+
-** vsetvli\s+zero,a\d+,e8,m1,ta,ma
+** li\s+a2,\d+
+** tail\s+memset
** )
-** vmv\.v\.x\s+v\d+,a1
-** vse8\.v\s+v\d+,0\(a0\)
-** ret
*/
void *
f1 (void *a, int const b)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
index 02de9a94cc47..25be694d248a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
@@ -5,17 +5,15 @@
#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
-/* Vectorise with no loop.
+/* Small memsets shouldn't be vectorised.
** f1:
** (
-** vsetivli\s+zero,\d+,e8,m1,ta,ma
+** sb\s+a1,0\(a0\)
+** ...
** |
-** li\s+a\d+,\d+
-** vsetvli\s+zero,a\d+,e8,m1,ta,ma
+** li\s+a2,\d+
+** tail\s+memset
** )
-** vmv\.v\.x\s+v\d+,a1
-** vse8\.v\s+v\d+,0\(a0\)
-** ret
*/
void *
f1 (void *a, int const b)
--
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