From 03e0010d71efedb4a5a9718a68fc4ffdd9e24f5b Mon Sep 17 00:00:00 2001
From: Jakub Jelinek <jakub@redhat.com>
Date: Tue, 1 Nov 2011 02:09:58 +0100
Subject: [PATCH] sse.md (fixuns_trunc<mode><sseintvecmodelower>2): New
expander.
* config/i386/sse.md (fixuns_trunc<mode><sseintvecmodelower>2): New
expander.
From-SVN: r180724
---
gcc/ChangeLog | 3 +++
gcc/config/i386/sse.md | 29 +++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 703c03d2561a..821e0e56bea2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
2011-11-01 Jakub Jelinek <jakub@redhat.com>
+ * config/i386/sse.md (fixuns_trunc<mode><sseintvecmodelower>2): New
+ expander.
+
* config/i386/sse.md (sseintvecmode): Remove duplicate modes.
(sseintvecmodelower): New mode iterator.
(floatv8siv8sf2, floatunsv4siv4sf2): Macroize into...
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 4bd9e6d42ec2..7d1cf293f281 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2322,6 +2322,35 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
+(define_expand "fixuns_trunc<mode><sseintvecmodelower>2"
+ [(set (match_dup 4)
+ (unspec:VF1
+ [(match_operand:VF1 1 "register_operand" "")
+ (match_dup 2)
+ (const_int 29)] UNSPEC_PCMP))
+ (set (match_dup 5)
+ (and:VF1 (match_dup 4) (match_dup 3)))
+ (set (match_dup 6)
+ (plus:VF1 (match_dup 1) (match_dup 5)))
+ (set (match_operand:<sseintvecmode> 0 "register_operand" "")
+ (fix:<sseintvecmode> (match_dup 6)))]
+ "TARGET_AVX"
+{
+ REAL_VALUE_TYPE MTWO32r, TWO31r;
+ int i;
+
+ real_ldexp (&TWO31r, &dconst1, 31);
+ operands[2] = const_double_from_real_value (TWO31r, SFmode);
+ operands[2] = ix86_build_const_vector (<MODE>mode, 1, operands[2]);
+ operands[2] = force_reg (<MODE>mode, operands[2]);
+ real_ldexp (&MTWO32r, &dconstm1, 32);
+ operands[3] = const_double_from_real_value (MTWO32r, SFmode);
+ operands[3] = ix86_build_const_vector (<MODE>mode, 1, operands[3]);
+ operands[3] = force_reg (<MODE>mode, operands[3]);
+ for (i = 4; i < 7; i++)
+ operands[i] = gen_reg_rtx (<MODE>mode);
+})
+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Parallel double-precision floating point conversion operations
--
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