From 06d50e2171f742c192a195afaf1f7eac000633a9 Mon Sep 17 00:00:00 2001
From: Ian Bolton <ian.bolton@arm.com>
Date: Fri, 24 May 2013 14:59:20 +0000
Subject: [PATCH] AArch64 - fix invalid assembler in testcase
From-SVN: r199294
---
gcc/testsuite/ChangeLog | 7 +++++++
gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c | 6 +++---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index cd0842df50c8..bf8ba0bb92b0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2013-05-24 Ian Bolton <ian.bolton@arm.com>
+
+ * gcc.target/aarch64/scalar_intrinsics.c
+ (force_simd): Use a valid instruction.
+ (test_vdupd_lane_s64): Pass a valid lane argument.
+ (test_vdupd_lane_u64): Likewise.
+
2013-05-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/57287
diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
index 7427c6217f8b..16537ce7d351 100644
--- a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
+++ b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -4,7 +4,7 @@
#include <arm_neon.h>
/* Used to force a variable to a SIMD register. */
-#define force_simd(V1) asm volatile ("mov %d0, %d1" \
+#define force_simd(V1) asm volatile ("mov %d0, %1.d[0]" \
: "=w"(V1) \
: "w"(V1) \
: /* No clobbers */);
@@ -228,13 +228,13 @@ test_vdups_lane_u32 (uint32x4_t a)
int64x1_t
test_vdupd_lane_s64 (int64x2_t a)
{
- return vdupd_lane_s64 (a, 2);
+ return vdupd_lane_s64 (a, 1);
}
uint64x1_t
test_vdupd_lane_u64 (uint64x2_t a)
{
- return vdupd_lane_u64 (a, 2);
+ return vdupd_lane_u64 (a, 1);
}
/* { dg-final { scan-assembler-times "\\tcmtst\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
--
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