diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 1374868eddfbc63ed2a9849eb18aafc7bff5a10c..08754be529e906ad94c6573e5fc270c530af53e4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7009,62 +7009,77 @@ riscv_print_operand (FILE *file, rtx op, int letter)
fputs (GET_RTX_NAME (reverse_condition (code)), file);
break;
- case 'A': {
- const enum memmodel model = memmodel_base (INTVAL (op));
- if (riscv_memmodel_needs_amo_acquire (model)
- && riscv_memmodel_needs_amo_release (model))
- fputs (".aqrl", file);
- else if (riscv_memmodel_needs_amo_acquire (model))
- fputs (".aq", file);
- else if (riscv_memmodel_needs_amo_release (model))
- fputs (".rl", file);
+ case 'A':
+ if (!CONST_INT_P (op))
+ output_operand_lossage ("invalid operand for '%%%c'", letter);
+ else
+ {
+ const enum memmodel model = memmodel_base (INTVAL (op));
+ if (riscv_memmodel_needs_amo_acquire (model)
+ && riscv_memmodel_needs_amo_release (model))
+ fputs (".aqrl", file);
+ else if (riscv_memmodel_needs_amo_acquire (model))
+ fputs (".aq", file);
+ else if (riscv_memmodel_needs_amo_release (model))
+ fputs (".rl", file);
+ }
break;
- }
- case 'I': {
- const enum memmodel model = memmodel_base (INTVAL (op));
- if (TARGET_ZTSO && model != MEMMODEL_SEQ_CST)
- /* LR ops only have an annotation for SEQ_CST in the Ztso mapping. */
- break;
- else if (model == MEMMODEL_SEQ_CST)
- fputs (".aqrl", file);
- else if (riscv_memmodel_needs_amo_acquire (model))
- fputs (".aq", file);
+ case 'I':
+ if (!CONST_INT_P (op))
+ output_operand_lossage ("invalid operand for '%%%c'", letter);
+ else
+ {
+ const enum memmodel model = memmodel_base (INTVAL (op));
+ if (TARGET_ZTSO && model != MEMMODEL_SEQ_CST)
+ /* LR ops only have an annotation for SEQ_CST in the Ztso mapping. */
+ break;
+ else if (model == MEMMODEL_SEQ_CST)
+ fputs (".aqrl", file);
+ else if (riscv_memmodel_needs_amo_acquire (model))
+ fputs (".aq", file);
+ }
break;
- }
- case 'J': {
- const enum memmodel model = memmodel_base (INTVAL (op));
- if (TARGET_ZTSO && model == MEMMODEL_SEQ_CST)
- /* SC ops only have an annotation for SEQ_CST in the Ztso mapping. */
- fputs (".rl", file);
- else if (TARGET_ZTSO)
- break;
- else if (riscv_memmodel_needs_amo_release (model))
- fputs (".rl", file);
+ case 'J':
+ if (!CONST_INT_P (op))
+ output_operand_lossage ("invalid operand for '%%%c'", letter);
+ else
+ {
+ const enum memmodel model = memmodel_base (INTVAL (op));
+ if (TARGET_ZTSO && model == MEMMODEL_SEQ_CST)
+ /* SC ops only have an annotation for SEQ_CST in the Ztso mapping. */
+ fputs (".rl", file);
+ else if (TARGET_ZTSO)
+ break;
+ else if (riscv_memmodel_needs_amo_release (model))
+ fputs (".rl", file);
+ }
break;
- }
case 'L':
- {
- const char *ntl_hint = NULL;
- switch (INTVAL (op))
- {
- case 0:
- ntl_hint = "ntl.all";
- break;
- case 1:
- ntl_hint = "ntl.pall";
- break;
- case 2:
- ntl_hint = "ntl.p1";
- break;
- }
+ if (!CONST_INT_P (op))
+ output_operand_lossage ("invalid operand for '%%%c'", letter);
+ else
+ {
+ const char *ntl_hint = NULL;
+ switch (INTVAL (op))
+ {
+ case 0:
+ ntl_hint = "ntl.all";
+ break;
+ case 1:
+ ntl_hint = "ntl.pall";
+ break;
+ case 2:
+ ntl_hint = "ntl.p1";
+ break;
+ }
- if (ntl_hint)
- asm_fprintf (file, "%s\n\t", ntl_hint);
+ if (ntl_hint)
+ asm_fprintf (file, "%s\n\t", ntl_hint);
+ }
break;
- }
case 'i':
if (code != REG)
@@ -7076,32 +7091,44 @@ riscv_print_operand (FILE *file, rtx op, int letter)
break;
case 'S':
- {
- rtx newop = GEN_INT (ctz_hwi (INTVAL (op)));
- output_addr_const (file, newop);
- break;
- }
+ if (!CONST_INT_P (op))
+ output_operand_lossage ("invalid operand for '%%%c'", letter);
+ else
+ {
+ rtx newop = GEN_INT (ctz_hwi (INTVAL (op)));
+ output_addr_const (file, newop);
+ }
+ break;
case 'T':
- {
- rtx newop = GEN_INT (ctz_hwi (~INTVAL (op)));
- output_addr_const (file, newop);
- break;
- }
+ if (!CONST_INT_P (op))
+ output_operand_lossage ("invalid operand for '%%%c'", letter);
+ else
+ {
+ rtx newop = GEN_INT (ctz_hwi (~INTVAL (op)));
+ output_addr_const (file, newop);
+ }
+ break;
case 'X':
- {
- int ival = INTVAL (op) + 1;
- rtx newop = GEN_INT (ctz_hwi (ival) + 1);
- output_addr_const (file, newop);
- break;
- }
+ if (!CONST_INT_P (op))
+ output_operand_lossage ("invalid operand for '%%%c'", letter);
+ else
+ {
+ int ival = INTVAL (op) + 1;
+ rtx newop = GEN_INT (ctz_hwi (ival) + 1);
+ output_addr_const (file, newop);
+ }
+ break;
case 'Y':
- {
- unsigned int imm = (UINTVAL (op) & 63);
- gcc_assert (imm <= 63);
- rtx newop = GEN_INT (imm);
- output_addr_const (file, newop);
- break;
- }
+ if (!CONST_INT_P (op))
+ output_operand_lossage ("invalid operand for '%%%c'", letter);
+ else
+ {
+ unsigned int imm = (UINTVAL (op) & 63);
+ gcc_assert (imm <= 63);
+ rtx newop = GEN_INT (imm);
+ output_addr_const (file, newop);
+ }
+ break;
case 'N':
{
if (!REG_P(op))
@@ -7119,7 +7146,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
else if (IN_RANGE (regno, V_REG_FIRST, V_REG_LAST))
offset = V_REG_FIRST;
else
- output_operand_lossage ("invalid register number for 'N' modifie");
+ output_operand_lossage ("invalid register number for 'N' modifier");
asm_fprintf (file, "%u", (regno - offset));
break;
diff --git a/gcc/testsuite/gcc.target/riscv/pr106544.c b/gcc/testsuite/gcc.target/riscv/pr106544.c
new file mode 100644
index 0000000000000000000000000000000000000000..6e449ee0c6b2a536226f0da7be5c03c4680c89d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106544.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto"} } */
+void f(int a)
+{
+ __asm("#%A0" : : "r"(a)); /* { dg-error "invalid 'asm': invalid operand" } */
+}