diff --git a/gcc/ira.c b/gcc/ira.c
index f0bdbc8cf56104ab99987c7c883d1dd2f0291b63..c32ecf814fdbd2c6eac5142125bb53caae103b6f 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -5566,6 +5566,15 @@ ira (FILE *f)
   if (warn_clobbered)
     generate_setjmp_warnings ();
 
+  /* update_equiv_regs can use reg classes of pseudos and they are set up in
+     register pressure sensitive scheduling and loop invariant motion and in
+     live range shrinking.  This info can become obsolete if we add new pseudos
+     since the last set up.  Recalculate it again if the new pseudos were
+     added.  */
+  if (resize_reg_info () && (flag_sched_pressure || flag_live_range_shrinkage
+			     || flag_ira_loop_pressure))
+    ira_set_pseudo_classes (true, ira_dump_file);
+
   init_alias_analysis ();
   loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
   reg_equiv = XCNEWVEC (struct equivalence, max_reg_num ());
@@ -5610,9 +5619,6 @@ ira (FILE *f)
       regstat_recompute_for_max_regno ();
     }
 
-  if (resize_reg_info () && flag_ira_loop_pressure)
-    ira_set_pseudo_classes (true, ira_dump_file);
-
   setup_reg_equiv ();
   grow_reg_equivs ();
   setup_reg_equiv_init ();
diff --git a/gcc/testsuite/gcc.target/i386/pr97684.c b/gcc/testsuite/gcc.target/i386/pr97684.c
new file mode 100644
index 0000000000000000000000000000000000000000..983bf535ad89320ece92bee25f0940f36a2a2c64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr97684.c
@@ -0,0 +1,24 @@
+/* PR rtl-optimization/97684 */
+/* { dg-do compile } */
+/* { dg-options "-O1 -flive-range-shrinkage -fschedule-insns -fselective-scheduling -funroll-all-loops -fno-web" } */
+
+void
+c5 (double);
+
+void
+g4 (int *n4)
+{
+  double lp = 0.0;
+  int fn;
+
+  for (fn = 0; fn < 18; ++fn)
+    {
+      int as;
+
+      as = __builtin_abs (n4[fn]);
+      if (as > lp)
+        lp = as;
+    }
+
+  c5 (lp);
+}