diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 047d0508a4915381eab121ee04e324c4cf46d10d..1a5967a24008a69bc2d559332ec3b6c023ec662b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,116 @@
+2022-08-29 David Faust <david.faust@oracle.com>
+
+ PR target/106745
+ * config/bpf/coreout.cc (bpf_core_get_sou_member_index): Fix
+ computation of index for anonymous members.
+
+2022-08-29 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/bpf/bpf.cc (bpf_target_macros): Define __bpf__ as a
+ target macro.
+
+2022-08-29 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/106748
+ * config/i386/i386-expand.cc
+ (ix86_avx256_split_vector_move_misalign): Handle E_V16BFmode.
+ * config/i386/sse.md (V_256H): Add V16BF.
+
+2022-08-29 Robin Dapp <rdapp@linux.ibm.com>
+
+ * config/s390/s390.cc (s390_address_cost): Declare.
+ (s390_hard_regno_nregs): Declare.
+ (s390_rtx_costs): Add handling for REG and MEM in SET.
+
+2022-08-29 Robin Dapp <rdapp@linux.ibm.com>
+
+ * config/s390/s390.cc (expand_perm_with_vpdi): Recognize swap pattern.
+ (is_reverse_perm_mask): New function.
+ (expand_perm_with_rot): Recognize reverse pattern.
+ (expand_perm_with_vstbrq): New function.
+ (expand_perm_with_vster): Use vler/vster for element reversal on z15.
+ (vectorize_vec_perm_const_1): Use.
+ (s390_vectorize_vec_perm_const): Add expand functions.
+ * config/s390/vx-builtins.md: Prefer vster over vler.
+
+2022-08-29 Robin Dapp <rdapp@linux.ibm.com>
+
+ * config/s390/s390.md: Remove UNSPEC_VEC_EXTRACT.
+ * config/s390/vector.md: Rewrite patterns to use vec_select.
+ * config/s390/vx-builtins.md (vec_scatter_element<V_HW_2:mode>_SI):
+ Likewise.
+
+2022-08-29 Robin Dapp <rdapp@linux.ibm.com>
+
+ PR target/100869
+ * config/s390/vector.md (@vpdi4_2<mode>): New pattern.
+ (rotl<mode>3_di): New pattern.
+ * config/s390/vx-builtins.md: Use vpdi and verll for reversing
+ elements.
+
+2022-08-29 Robin Dapp <rdapp@linux.ibm.com>
+
+ * config/s390/s390.cc (s390_issue_rate): Add z15.
+
+2022-08-29 Robin Dapp <rdapp@linux.ibm.com>
+
+ * common/config/s390/s390-common.cc: Enable -funroll-loops and
+ -munroll-only-small-loops for OPT_LEVELS_2_PLUS_SPEED_ONLY.
+ * config/s390/s390.cc (s390_loop_unroll_adjust): Do not unroll
+ loops larger than 12 instructions.
+ (s390_override_options_after_change): Set unroll options.
+ (s390_option_override_internal): Likewise.
+ * config/s390/s390.opt: Document munroll-only-small-loops.
+
+2022-08-29 Richard Biener <rguenther@suse.de>
+
+ * gimple-predicate-analysis.cc (is_loop_exit,
+ find_control_equiv_block): Inline into single caller ...
+ (uninit_analysis::init_use_preds): ... here and refactor.
+
+2022-08-29 Richard Biener <rguenther@suse.de>
+
+ * gimple-predicate-analysis.cc (compute_control_dep_chain):
+ Inline is_loop_exit and refactor, add comment about
+ loop exits.
+
+2022-08-29 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/riscv.cc (riscv_frame_info): Introduce `reset(void)`;
+ (riscv_frame_info::reset(void)): New.
+ (riscv_compute_frame_info): Use riscv_frame_info::reset instead
+ of memset when clean frame.
+
+2022-08-29 zhongjuzhe <juzhe.zhong@rivai.ai>
+
+ * config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): New function.
+ (riscv_classify_address): Disallow PLUS/LO_SUM/CONST_INT address types for RVV.
+ (riscv_address_insns): Add RVV modes condition.
+ (riscv_binary_cost): Ditto.
+ (riscv_rtx_costs): Adjust cost for RVV.
+ (riscv_secondary_memory_needed): Add RVV modes condition.
+ (riscv_hard_regno_nregs): Add RVV register allocation.
+ (riscv_hard_regno_mode_ok): Add RVV register allocation.
+ (riscv_class_max_nregs): Add RVV register allocation.
+ * config/riscv/riscv.h (DWARF_FRAME_REGNUM): Add VL/VTYPE and vector registers in Dwarf.
+ (UNITS_PER_V_REG): New macro.
+ (FIRST_PSEUDO_REGISTER): Adjust first pseudo num for RVV.
+ (V_REG_FIRST): New macro.
+ (V_REG_LAST): Ditto.
+ (V_REG_NUM): Ditto.
+ (V_REG_P): Ditto.
+ (VL_REG_P): Ditto.
+ (VTYPE_REG_P): Ditto.
+ (RISCV_DWARF_VL): Ditto.
+ (RISCV_DWARF_VTYPE): Ditto.
+ (enum reg_class): Add RVV register types.
+ (REG_CLASS_CONTENTS): Add RVV register types.
+ * config/riscv/riscv.md: Add VL/VTYPE register number constants.
+
+2022-08-29 zhongjuzhe <juzhe.zhong@rivai.ai>
+
+ * config/riscv/riscv.md: Add new type for vector instructions.
+
2022-08-28 Peter Bergner <bergner@linux.ibm.com>
PR target/106017
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 85ed11f60d39c715f6cdd72b092aed573605fe31..41f0d849079eb32f242baa787ee09d7759bd540b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20220829
+20220830
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 71fb7dbb18a11b10cb8ed5536592541a358e97f6..b59685c37413b70b34e9184717f6eb8fb370e354 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,9 @@
+2022-08-29 Marek Polacek <polacek@redhat.com>
+
+ PR c++/106712
+ * decl.cc (grokdeclarator): Reverse the order of arguments to
+ attr_chainon.
+
2022-08-26 Marek Polacek <polacek@redhat.com>
PR c++/81159
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9fadacfb5901fe390f45a892e7b1867843bedd26..33006b2f8b2f98d9f68e9ab4164e4ce9e494d3a2 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,54 @@
+2022-08-29 Marek Polacek <polacek@redhat.com>
+
+ PR c++/106712
+ * g++.dg/cpp0x/gen-attrs-77.C: New test.
+
+2022-08-29 David Faust <david.faust@oracle.com>
+
+ PR target/106745
+ * gcc.target/bpf/core-pr106745.c: New test.
+
+2022-08-29 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/106748
+ * gcc.target/i386/pr106748.c: New test.
+
+2022-08-29 Xi Ruoyao <xry111@xry111.site>
+
+ * gcc.target/loongarch/func-call-medium-1.c: Refine test
+ depending on __tls_get_addr with { target tls_native }.
+ * gcc.target/loongarch/func-call-medium-2.c: Likewise.
+ * gcc.target/loongarch/func-call-medium-3.c: Likewise.
+ * gcc.target/loongarch/func-call-medium-4.c: Likewise.
+ * gcc.target/loongarch/func-call-medium-5.c: Likewise.
+ * gcc.target/loongarch/func-call-medium-6.c: Likewise.
+ * gcc.target/loongarch/func-call-medium-7.c: Likewise.
+ * gcc.target/loongarch/func-call-medium-8.c: Likewise.
+ * gcc.target/loongarch/tls-gd-noplt.c: Likewise.
+
+2022-08-29 Robin Dapp <rdapp@linux.ibm.com>
+
+ * gcc.target/s390/vector/vec-sum-across-no-lower-subreg-1.c: New test.
+
+2022-08-29 Robin Dapp <rdapp@linux.ibm.com>
+
+ * gcc.target/s390/vector/vperm-rev-z14.c: New test.
+ * gcc.target/s390/vector/vperm-rev-z15.c: New test.
+ * gcc.target/s390/zvector/vec-reve-store-byte.c: Adjust test
+ expectation.
+
+2022-08-29 Robin Dapp <rdapp@linux.ibm.com>
+
+ * gcc.target/s390/zvector/vec-reve-int-long.c: New test.
+
+2022-08-29 Robin Dapp <rdapp@linux.ibm.com>
+
+ * gcc.target/s390/vector/vec-copysign.c: Do not unroll.
+ * gcc.target/s390/zvector/autovec-double-quiet-uneq.c: Dito.
+ * gcc.target/s390/zvector/autovec-double-signaling-ltgt.c: Dito.
+ * gcc.target/s390/zvector/autovec-float-quiet-uneq.c: Dito.
+ * gcc.target/s390/zvector/autovec-float-signaling-ltgt.c: Dito.
+
2022-08-28 Peter Bergner <bergner@linux.ibm.com>
PR target/106017