From 0cf251fba0f0a374225a81021af5ec6c6ccceb5b Mon Sep 17 00:00:00 2001
From: Jakub Jelinek <jakub@redhat.com>
Date: Tue, 19 Dec 2023 10:24:33 +0100
Subject: [PATCH] i386: Fix mmx.md signbit expanders [PR112816]
Apparently when looking for "signbit<mode>2" vector expanders, I've only
looked at sse.md and forgot mmx.md, which has another one and the
following patch still ICEd.
2023-12-19 Jakub Jelinek <jakub@redhat.com>
PR target/112816
* config/i386/mmx.md (signbitv2sf2): Force operands[1] into a REG.
* gcc.target/i386/sse2-pr112816-2.c: New test.
(cherry picked from commit 80e1375ed7a7a05a5a60a57e72c5ad5eba005798)
---
gcc/config/i386/mmx.md | 5 ++++-
gcc/testsuite/gcc.target/i386/sse2-pr112816-2.c | 16 ++++++++++++++++
2 files changed, 20 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/sse2-pr112816-2.c
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 18dae03ad0a4..87f9da6ca06f 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1268,7 +1268,10 @@
(match_operand:V2SF 1 "register_operand") 0)
(match_dup 2)))]
"TARGET_MMX_WITH_SSE"
- "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (V2SFmode)-1);")
+{
+ operands[1] = force_reg (V2SFmode, operands[1]);
+ operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (V2SFmode)-1);
+})
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
diff --git a/gcc/testsuite/gcc.target/i386/sse2-pr112816-2.c b/gcc/testsuite/gcc.target/i386/sse2-pr112816-2.c
new file mode 100644
index 000000000000..2bfae8fa58e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse2-pr112816-2.c
@@ -0,0 +1,16 @@
+/* PR target/112816 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#define N 2
+struct S { float x[N]; };
+struct T { int x[N]; };
+
+struct T
+foo (struct S x)
+{
+ struct T res;
+ for (int i = 0; i < N; ++i)
+ res.x[i] = __builtin_signbit (x.x[i]) ? -1 : 0;
+ return res;
+}
--
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