From 0de86a92286fb5a6ddbe867e0f88b707e6e5ab29 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C3=BCrgen=20Urban?= <JuergenUrban@gmx.de>
Date: Sun, 16 Jun 2013 19:31:24 +0000
Subject: [PATCH] mips.h (ISA_HAS_MUL3): Include TARGET_MIPS5900.
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gcc/
2013-06-16 Jürgen Urban <JuergenUrban@gmx.de>
* config/mips/mips.h (ISA_HAS_MUL3): Include TARGET_MIPS5900.
(ISA_HAS_MULT, ISA_HAS_DMULT, ISA_HAS_DIV, ISA_HAS_DDIV): New macros.
* config/mips/mips.md (mul<mode>3, mul<mode>3_internal)
(mul<mode>3_r4000): Require ISA_HAS_<D>MULT.
(mul<mode>3_mul3): Handle TARGET_MIPS5900.
(mulsidi3_64bit_dmul): Remove redundant TARGET_64BIT test.
(<su>muldi3_highpart, <su>muldi3_highpart_internal, <u>mulditi3)
(<u>mulditi3_internal, <u>mulditi3_r4000): Require ISA_HAS_DMULT
instead of TARGET_64BIT.
(divmod<mode>4, udivmod<mode>4, <u>divmod<GPR:mode>4_hilo_<HILO:mode>):
Require ISA_HAS_<D>DIV.
libgcc/
2013-06-16 Jürgen Urban <JuergenUrban@gmx.de>
* config/mips/lib2funcs.c: New file.
* config/mips/t-mips (LIB2ADD_ST): Add it.
From-SVN: r200140
---
gcc/ChangeLog | 14 +++++++++++
gcc/config/mips/mips.h | 17 +++++++++++++
gcc/config/mips/mips.md | 26 ++++++++++----------
libgcc/ChangeLog | 5 ++++
libgcc/config/mips/lib2funcs.c | 44 ++++++++++++++++++++++++++++++++++
libgcc/config/mips/t-mips | 2 ++
6 files changed, 95 insertions(+), 13 deletions(-)
create mode 100644 libgcc/config/mips/lib2funcs.c
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9f97845f85e3..7e28ee0b20ae 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2013-06-16 Jürgen Urban <JuergenUrban@gmx.de>
+
+ * config/mips/mips.h (ISA_HAS_MUL3): Include TARGET_MIPS5900.
+ (ISA_HAS_MULT, ISA_HAS_DMULT, ISA_HAS_DIV, ISA_HAS_DDIV): New macros.
+ * config/mips/mips.md (mul<mode>3, mul<mode>3_internal)
+ (mul<mode>3_r4000): Require ISA_HAS_<D>MULT.
+ (mul<mode>3_mul3): Handle TARGET_MIPS5900.
+ (mulsidi3_64bit_dmul): Remove redundant TARGET_64BIT test.
+ (<su>muldi3_highpart, <su>muldi3_highpart_internal, <u>mulditi3)
+ (<u>mulditi3_internal, <u>mulditi3_r4000): Require ISA_HAS_DMULT
+ instead of TARGET_64BIT.
+ (divmod<mode>4, udivmod<mode>4, <u>divmod<GPR:mode>4_hilo_<HILO:mode>):
+ Require ISA_HAS_<D>DIV.
+
2013-06-16 Richard Sandiford <rdsandiford@googlemail.com>
* config.gcc (mips*-mti-linux*, mips64*-*-linux*, mipsisa64*-*-linux*)
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 479bdd4531ce..ff631c1a30b6 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -807,6 +807,7 @@ struct mips_cpu_info {
#define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
+ || TARGET_MIPS5900 \
|| TARGET_MIPS7000 \
|| TARGET_MIPS9000 \
|| TARGET_MAD \
@@ -821,6 +822,22 @@ struct mips_cpu_info {
&& TARGET_OCTEON \
&& !TARGET_MIPS16)
+/* ISA supports instructions DMULT and DMULTU. */
+#define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
+
+/* ISA supports instructions MULT and MULTU.
+ This is always true, but the macro is needed for ISA_HAS_<D>MULT
+ in mips.md. */
+#define ISA_HAS_MULT (1)
+
+/* ISA supports instructions DDIV and DDIVU. */
+#define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
+
+/* ISA supports instructions DIV and DIVU.
+ This is always true, but the macro is needed for ISA_HAS_<D>DIV
+ in mips.md. */
+#define ISA_HAS_DIV (1)
+
#define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
|| TARGET_LOONGSON_3A) \
&& !TARGET_MIPS16)
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index ed60d0e44f21..ce322d8bc360 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1468,7 +1468,7 @@
[(set (match_operand:GPR 0 "register_operand")
(mult:GPR (match_operand:GPR 1 "register_operand")
(match_operand:GPR 2 "register_operand")))]
- ""
+ "ISA_HAS_<D>MULT"
{
rtx lo;
@@ -1514,7 +1514,7 @@
{
if (which_alternative == 1)
return "<d>mult\t%1,%2";
- if (<MODE>mode == SImode && TARGET_MIPS3900)
+ if (<MODE>mode == SImode && (TARGET_MIPS3900 || TARGET_MIPS5900))
return "mult\t%0,%1,%2";
return "<d>mul\t%0,%1,%2";
}
@@ -1548,7 +1548,7 @@
[(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
(mult:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))]
- "!TARGET_FIX_R4000"
+ "ISA_HAS_<D>MULT && !TARGET_FIX_R4000"
"<d>mult\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "<MODE>")])
@@ -1558,7 +1558,7 @@
(mult:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))
(clobber (match_scratch:GPR 3 "=l"))]
- "TARGET_FIX_R4000"
+ "ISA_HAS_<D>MULT && TARGET_FIX_R4000"
"<d>mult\t%1,%2\;mflo\t%0"
[(set_attr "type" "imul")
(set_attr "mode" "<MODE>")
@@ -2025,7 +2025,7 @@
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
(sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
(clobber (match_scratch:DI 3 "=l"))]
- "TARGET_64BIT && ISA_HAS_DMUL3"
+ "ISA_HAS_DMUL3"
"dmul\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "DI")])
@@ -2179,7 +2179,7 @@
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
(any_extend:TI (match_operand:DI 2 "register_operand")))
(const_int 64))))]
- "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+ "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
{
if (TARGET_MIPS16)
emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
@@ -2198,7 +2198,7 @@
(any_extend:TI (match_operand:DI 2 "register_operand" "d")))
(const_int 64))))
(clobber (match_scratch:DI 3 "=l"))]
- "TARGET_64BIT
+ "ISA_HAS_DMULT
&& !TARGET_MIPS16
&& !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
{ return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
@@ -2234,7 +2234,7 @@
[(set (match_operand:TI 0 "register_operand")
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
(any_extend:TI (match_operand:DI 2 "register_operand"))))]
- "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+ "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
{
rtx hilo;
@@ -2256,7 +2256,7 @@
[(set (match_operand:TI 0 "muldiv_target_operand" "=x")
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
(any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
- "TARGET_64BIT
+ "ISA_HAS_DMULT
&& !TARGET_FIX_R4000
&& !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
"dmult<u>\t%1,%2"
@@ -2268,7 +2268,7 @@
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
(any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
(clobber (match_scratch:TI 3 "=x"))]
- "TARGET_64BIT
+ "ISA_HAS_DMULT
&& TARGET_FIX_R4000
&& !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
"dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
@@ -2564,7 +2564,7 @@
(set (match_operand:GPR 3 "register_operand" "=d")
(mod:GPR (match_dup 1)
(match_dup 2)))]
- "!TARGET_FIX_VR4120"
+ "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
"#"
"&& ((TARGET_MIPS16 && cse_not_expected) || reload_completed)"
[(const_int 0)]
@@ -2587,7 +2587,7 @@
(set (match_operand:GPR 3 "register_operand" "=d")
(umod:GPR (match_dup 1)
(match_dup 2)))]
- ""
+ "ISA_HAS_<D>DIV"
"#"
"(TARGET_MIPS16 && cse_not_expected) || reload_completed"
[(const_int 0)]
@@ -2633,7 +2633,7 @@
[(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d"))]
UNSPEC_SET_HILO))]
- ""
+ "ISA_HAS_<GPR:D>DIV"
{ return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
[(set_attr "type" "idiv")
(set_attr "mode" "<GPR:MODE>")])
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 832b4256e698..56b346392378 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-06-16 Jürgen Urban <JuergenUrban@gmx.de>
+
+ * config/mips/lib2funcs.c: New file.
+ * config/mips/t-mips (LIB2ADD_ST): Add it.
+
2013-06-09 Oleg Endo <olegendo@gcc.gnu.org>
PR target/6526
diff --git a/libgcc/config/mips/lib2funcs.c b/libgcc/config/mips/lib2funcs.c
new file mode 100644
index 000000000000..85d9f17a4cdf
--- /dev/null
+++ b/libgcc/config/mips/lib2funcs.c
@@ -0,0 +1,44 @@
+/* libgcc routines for MIPS
+ Copyright (C) 2013 Free Software Foundation, Inc.
+ DMULT/DDIV replacement support by Juergen Urban, JuergenUrban@gmx.de.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+<http://www.gnu.org/licenses/>. */
+
+#if defined(__mips64) && defined(_MIPS_ARCH_R5900)
+
+/* Build DI version of libgcc functions. */
+#define LIBGCC2_UNITS_PER_WORD 4
+
+/* The following function is needed when !ISA_HAS_DMULT. */
+#define L_muldi3
+
+/* The following functions are needed when !ISA_HAS_DDIV. */
+#define L_divdi3
+#define L_moddi3
+#define L_udivdi3
+#define L_umoddi3
+#define L_udivmoddi4
+
+/* Use generic definition of functions. */
+#include "libgcc2.c"
+
+#endif
diff --git a/libgcc/config/mips/t-mips b/libgcc/config/mips/t-mips
index 719c062ef0d4..ed5550e70482 100644
--- a/libgcc/config/mips/t-mips
+++ b/libgcc/config/mips/t-mips
@@ -4,3 +4,5 @@ FPBIT = true
FPBIT_CFLAGS = -DQUIET_NAN_NEGATED
DPBIT = true
DPBIT_CFLAGS = -DQUIET_NAN_NEGATED
+
+LIB2ADD_ST += $(srcdir)/config/mips/lib2funcs.c
--
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