From 0f5a42d41b46b746c6f77374d76a3b918a1e2b57 Mon Sep 17 00:00:00 2001
From: "Hu, Lin1" <lin1.hu@intel.com>
Date: Mon, 19 Aug 2024 10:08:58 +0800
Subject: [PATCH] AVX10.2 ymm rounding: Support vcvtps2{,u}{dq,qq} intrins
gcc/ChangeLog:
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V8SI_FTYPE_V8SF_V8SI_UQI_INT, V4DI_FTYPE_V4SF_V4DI_UQI_INT.
* config/i386/sse.md
(<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>):
Extend to round.
(<mask_codefor><avx512>_fixuns_notrunc<sf2simodelower><mode><mask_name><round_name>):
Add round condition check.
* config/i386/subst.md (round_constraint4): New.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-1.c: Add test.
---
gcc/config/i386/avx10_2roundingintrin.h | 226 ++++++++++++++++++
gcc/config/i386/i386-builtin-types.def | 2 +
gcc/config/i386/i386-builtin.def | 4 +
gcc/config/i386/i386-expand.cc | 2 +
gcc/config/i386/sse.md | 10 +-
gcc/config/i386/subst.md | 1 +
gcc/testsuite/gcc.target/i386/avx-1.c | 4 +
.../gcc.target/i386/avx10_2-rounding-1.c | 32 +++
gcc/testsuite/gcc.target/i386/sse-13.c | 4 +
gcc/testsuite/gcc.target/i386/sse-14.c | 12 +
gcc/testsuite/gcc.target/i386/sse-22.c | 12 +
gcc/testsuite/gcc.target/i386/sse-23.c | 4 +
12 files changed, 308 insertions(+), 5 deletions(-)
diff --git a/gcc/config/i386/avx10_2roundingintrin.h b/gcc/config/i386/avx10_2roundingintrin.h
index bc3f92a7d1ae..fca10a6b586f 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -863,6 +863,146 @@ _mm256_maskz_cvtx_roundps_ph (__mmask8 __U, __m256 __A, const int __R)
(__mmask8) __U,
__R);
}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundps_epi32 (__m256 __A, const int __R)
+{
+ return
+ (__m256i) __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) __A,
+ (__v8si)
+ _mm256_undefined_si256 (),
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundps_epi32 (__m256i __W, __mmask8 __U, __m256 __A,
+ const int __R)
+{
+ return (__m256i) __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) __A,
+ (__v8si) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundps_epi32 (__mmask8 __U, __m256 __A, const int __R)
+{
+ return
+ (__m256i) __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) __A,
+ (__v8si)
+ _mm256_setzero_si256 (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundps_epi64 (__m128 __A, const int __R)
+{
+ return
+ (__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) __A,
+ (__v4di)
+ _mm256_setzero_si256 (),
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundps_epi64 (__m256i __W, __mmask8 __U, __m128 __A,
+ const int __R)
+{
+ return (__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) __A,
+ (__v4di) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundps_epi64 (__mmask8 __U, __m128 __A, const int __R)
+{
+ return
+ (__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) __A,
+ (__v4di)
+ _mm256_setzero_si256 (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundps_epu32 (__m256 __A, const int __R)
+{
+ return
+ (__m256i) __builtin_ia32_cvtps2udq256_mask_round ((__v8sf) __A,
+ (__v8si)
+ _mm256_undefined_si256 (),
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundps_epu32 (__m256i __W, __mmask8 __U, __m256 __A,
+ const int __R)
+{
+ return (__m256i) __builtin_ia32_cvtps2udq256_mask_round ((__v8sf) __A,
+ (__v8si) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundps_epu32 (__mmask8 __U, __m256 __A, const int __R)
+{
+ return
+ (__m256i) __builtin_ia32_cvtps2udq256_mask_round ((__v8sf) __A,
+ (__v8si)
+ _mm256_setzero_si256 (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundps_epu64 (__m128 __A, const int __R)
+{
+ return
+ (__m256i) __builtin_ia32_cvtps2uqq256_mask_round ((__v4sf) __A,
+ (__v4di)
+ _mm256_setzero_si256 (),
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundps_epu64 (__m256i __W, __mmask8 __U, __m128 __A,
+ const int __R)
+{
+ return (__m256i) __builtin_ia32_cvtps2uqq256_mask_round ((__v4sf) __A,
+ (__v4di) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundps_epu64 (__mmask8 __U, __m128 __A, const int __R)
+{
+ return
+ (__m256i) __builtin_ia32_cvtps2uqq256_mask_round ((__v4sf) __A,
+ (__v4di)
+ _mm256_setzero_si256 (),
+ (__mmask8) __U,
+ __R);
+}
#else
#define _mm256_add_round_pd(A, B, R) \
((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \
@@ -1359,6 +1499,92 @@ _mm256_maskz_cvtx_roundps_ph (__mmask8 __U, __m256 __A, const int __R)
(_mm_setzero_ph ()), \
(__mmask8) (U), \
(R)))
+
+#define _mm256_cvt_roundps_epi32(A, R) \
+ ((__m256i) \
+ __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) (A), \
+ (__v8si) \
+ (_mm256_undefined_si256 ()), \
+ (__mmask8) (-1), \
+ (R)))
+
+#define _mm256_mask_cvt_roundps_epi32(W, U, A, R) \
+ ((__m256i) __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) (A), \
+ (__v8si) (W), \
+ (__mmask8) (U), \
+ (R)))
+
+#define _mm256_maskz_cvt_roundps_epi32(U, A, R) \
+ ((__m256i) \
+ __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) (A), \
+ (__v8si) \
+ (_mm256_setzero_si256 ()), \
+ (__mmask8) (U), \
+ (R)))
+
+#define _mm256_cvt_roundps_epi64(A, R) \
+ ((__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) (A), \
+ (__v4di) \
+ (_mm256_setzero_si256 ()), \
+ (__mmask8) (-1), \
+ (R)))
+
+#define _mm256_mask_cvt_roundps_epi64(W, U, A, R) \
+ ((__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) (A), \
+ (__v4di) (W), \
+ (__mmask8) (U), \
+ (R)))
+
+#define _mm256_maskz_cvt_roundps_epi64(U, A, R) \
+ ((__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) (A), \
+ (__v4di) \
+ (_mm256_setzero_si256 ()), \
+ (__mmask8) (U), \
+ (R)))
+
+#define _mm256_cvt_roundps_epu32(A, R) \
+ ((__m256i) \
+ __builtin_ia32_cvtps2udq256_mask_round ((__v8sf) (A), \
+ (__v8si) \
+ (_mm256_undefined_si256 ()), \
+ (__mmask8) (-1), \
+ (R)))
+
+#define _mm256_mask_cvt_roundps_epu32(W, U, A, R) \
+ ((__m256i) __builtin_ia32_cvtps2udq256_mask_round ((__v8sf) (A), \
+ (__v8si) (W), \
+ (__mmask8) (U), \
+ (R)))
+
+#define _mm256_maskz_cvt_roundps_epu32(U, A, R) \
+ ((__m256i) \
+ __builtin_ia32_cvtps2udq256_mask_round ((__v8sf) (A), \
+ (__v8si) \
+ (_mm256_setzero_si256 ()), \
+ (__mmask8) (U), \
+ (R)))
+
+#define _mm256_cvt_roundps_epu64(B, R) \
+ ((__m256i) \
+ __builtin_ia32_cvtps2uqq256_mask_round ((__v4sf) (B), \
+ (__v4di) \
+ (_mm256_setzero_si256 ()), \
+ (__mmask8) (-1), \
+ (R)))
+
+#define _mm256_mask_cvt_roundps_epu64(W, U, A, R) \
+ ((__m256i) __builtin_ia32_cvtps2uqq256_mask_round ((__v4sf) (A), \
+ (__v4di) (W), \
+ (__mmask8) (U), \
+ (R)))
+
+#define _mm256_maskz_cvt_roundps_epu64(U, A, R) \
+ ((__m256i) \
+ __builtin_ia32_cvtps2uqq256_mask_round ((__v4sf) (A), \
+ (__v4di) \
+ (_mm256_setzero_si256 ()), \
+ (__mmask8) (U), \
+ (R)))
#endif
#ifdef __DISABLE_AVX10_2_256__
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index b850ee0c2f61..111d6e7651c0 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1434,3 +1434,5 @@ DEF_FUNCTION_TYPE (V4DI, V8HF, V4DI, UQI, INT)
DEF_FUNCTION_TYPE (V16HI, V16HF, V16HI, UHI, INT)
DEF_FUNCTION_TYPE (V4DF, V4SF, V4DF, UQI, INT)
DEF_FUNCTION_TYPE (V8HF, V8SF, V8HF, UQI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SF, V8SI, UQI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4SF, V4DI, UQI, INT)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 2a6c46f17a00..b623be7b742a 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3344,6 +3344,10 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtph2uw_v16hi_mask
BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtph2w_v16hi_mask_round, "__builtin_ia32_vcvtph2w256_mask_round", IX86_BUILTIN_VCVTPH2W256_MASK_ROUND, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx_cvtps2pd256_mask_round, "__builtin_ia32_vcvtps2pd256_mask_round", IX86_BUILTIN_VCVTPS2PD256_MASK_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_UQI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtps2ph_v8sf_mask_round, "__builtin_ia32_vcvtps2phx256_mask_round", IX86_BUILTIN_VCVTPS2PHX256_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V8SF_V8HF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx_fix_notruncv8sfv8si_mask_round, "__builtin_ia32_vcvtps2dq256_mask_round", IX86_BUILTIN_VCVTPS2DQ256_MASK_ROUND, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512dq_cvtps2qqv4di_mask_round, "__builtin_ia32_cvtps2qq256_mask_round", IX86_BUILTIN_VCVTPS2QQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fixuns_notruncv8sfv8si_mask_round, "__builtin_ia32_cvtps2udq256_mask_round", IX86_BUILTIN_VCVTPS2UDQ256_MASK_ROUND, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512dq_cvtps2uqqv4di_mask_round, "__builtin_ia32_cvtps2uqq256_mask_round", IX86_BUILTIN_VCVTPS2UQQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI_INT)
BDESC_END (ROUND_ARGS, MULTI_ARG)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 10318a76fd13..10587f8195ed 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -12404,11 +12404,13 @@ ix86_expand_round_builtin (const struct builtin_description *d,
case V16SF_FTYPE_V16HI_V16SF_HI_INT:
case V8SF_FTYPE_V8SI_V8SF_UQI_INT:
case V8SF_FTYPE_V8HF_V8SF_UQI_INT:
+ case V8SI_FTYPE_V8SF_V8SI_UQI_INT:
case V8SI_FTYPE_V8HF_V8SI_UQI_INT:
case V4DF_FTYPE_V4SF_V4DF_UQI_INT:
case V4DF_FTYPE_V8HF_V4DF_UQI_INT:
case V4DI_FTYPE_V8HF_V4DI_UQI_INT:
case V4DI_FTYPE_V4DF_V4DI_UQI_INT:
+ case V4DI_FTYPE_V4SF_V4DI_UQI_INT:
case V2DF_FTYPE_V2DF_V2DF_V2DF_INT:
case V4SI_FTYPE_V4DF_V4SI_UQI_INT:
case V4SF_FTYPE_V4DF_V4SF_UQI_INT:
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index cf27af27a5a8..e67ea40b70d7 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8412,13 +8412,13 @@
(define_mode_attr sf2simodelower
[(V16SI "v16sf") (V8SI "v8sf") (V4SI "v4sf")])
-(define_insn "<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>"
+(define_insn "<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name><round_name>"
[(set (match_operand:VI4_AVX 0 "register_operand" "=v")
(unspec:VI4_AVX
- [(match_operand:<ssePSmode> 1 "vector_operand" "vBm")]
+ [(match_operand:<ssePSmode> 1 "<round_nimm_predicate>" "<round_constraint4>")]
UNSPEC_FIX_NOTRUNC))]
- "TARGET_SSE2 && <mask_mode512bit_condition>"
- "%vcvtps2dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ "TARGET_SSE2 && <mask_mode512bit_condition> && <round_mode_condition>"
+ "%vcvtps2dq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set (attr "prefix_data16")
(if_then_else
@@ -8444,7 +8444,7 @@
(unspec:VI4_AVX512VL
[(match_operand:<ssePSmode> 1 "nonimmediate_operand" "<round_constraint>")]
UNSPEC_UNSIGNED_FIX_NOTRUNC))]
- "TARGET_AVX512F"
+ "TARGET_AVX512F && <round_mode_condition>"
"vcvtps2udq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md
index 7bb25d19eb52..3d0979ba18af 100644
--- a/gcc/config/i386/subst.md
+++ b/gcc/config/i386/subst.md
@@ -203,6 +203,7 @@
(define_subst_attr "bcst_round_constraint" "round" "vmBr" "v")
(define_subst_attr "round_constraint2" "round" "m" "v")
(define_subst_attr "round_constraint3" "round" "rm" "r")
+(define_subst_attr "round_constraint4" "round" "vBm" "v")
(define_subst_attr "round_nimm_predicate" "round" "vector_operand" "register_operand")
(define_subst_attr "bcst_round_nimm_predicate" "round" "bcst_vector_operand" "register_operand")
(define_subst_attr "round_nimm_scalar_predicate" "round" "nonimmediate_operand" "register_operand")
diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c
index 5eaad5c5250c..f9424dedf404 100644
--- a/gcc/testsuite/gcc.target/i386/avx-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx-1.c
@@ -868,6 +868,10 @@
#define __builtin_ia32_vcvtph2w256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2w256_mask_round(A, B, C, 8)
#define __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, 8)
#define __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, 8)
+#define __builtin_ia32_vcvtps2dq256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2dq256_mask_round(A, B, C, 8)
+#define __builtin_ia32_cvtps2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2qq256_mask_round(A, B, C, 8)
+#define __builtin_ia32_cvtps2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2udq256_mask_round(A, B, C, 8)
+#define __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, 8)
#include <wmmintrin.h>
#include <immintrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-1.c b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-1.c
index c35c667569a6..d0a0100e6c8c 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-1.c
@@ -72,6 +72,18 @@
/* { dg-final { scan-assembler-times "vcvtps2phxy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtps2phx\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtps2phx\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2dq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2dq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2dq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2qq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2qq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2qq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2udq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2udq\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2udq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2uqq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2uqq\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2uqq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
@@ -218,3 +230,23 @@ avx10_2_test_9 (void)
hxh = _mm256_mask_cvtx_roundps_ph (hxh, m8, x, 8);
hxh = _mm256_maskz_cvtx_roundps_ph (m8, x, 11);
}
+
+void extern
+avx10_2_test_10 (void)
+{
+ xi = _mm256_cvt_roundps_epi32 (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+ xi = _mm256_mask_cvt_roundps_epi32 (xi, m8, x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+ xi = _mm256_maskz_cvt_roundps_epi32 (m8, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+
+ xi = _mm256_cvt_roundps_epi64 (hx, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+ xi = _mm256_mask_cvt_roundps_epi64 (xi, m8, hx, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+ xi = _mm256_maskz_cvt_roundps_epi64 (m8, hx, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+
+ xi = _mm256_cvt_roundps_epu32 (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+ xi = _mm256_mask_cvt_roundps_epu32 (xi, m8, x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+ xi = _mm256_maskz_cvt_roundps_epu32 (m8, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+
+ xi = _mm256_cvt_roundps_epu64 (hx, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+ xi = _mm256_mask_cvt_roundps_epu64 (xi, m8, hx, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+ xi = _mm256_maskz_cvt_roundps_epu64 (m8, hx, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index 2c91c6626887..90547e480dea 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -875,5 +875,9 @@
#define __builtin_ia32_vcvtph2w256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2w256_mask_round(A, B, C, 8)
#define __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, 8)
#define __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, 8)
+#define __builtin_ia32_vcvtps2dq256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2dq256_mask_round(A, B, C, 8)
+#define __builtin_ia32_cvtps2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2qq256_mask_round(A, B, C, 8)
+#define __builtin_ia32_cvtps2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2udq256_mask_round(A, B, C, 8)
+#define __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, 8)
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
index 8f3271048ad1..2d55185bffc9 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1039,6 +1039,10 @@ test_1 (_mm256_cvt_roundph_epu16, __m256i, __m256h, 8)
test_1 (_mm256_cvt_roundph_epi16, __m256i, __m256h, 8)
test_1 (_mm256_cvt_roundps_pd, __m256d, __m128, 8)
test_1 (_mm256_cvtx_roundps_ph, __m128h, __m256, 8)
+test_1 (_mm256_cvt_roundps_epi32, __m256i, __m256, 9)
+test_1 (_mm256_cvt_roundps_epu32, __m256i, __m256, 9)
+test_1 (_mm256_cvt_roundps_epi64, __m256i, __m128, 8)
+test_1 (_mm256_cvt_roundps_epu64, __m256i, __m128, 8)
test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9)
test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8)
test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9)
@@ -1061,6 +1065,10 @@ test_2 (_mm256_maskz_cvt_roundph_epu16, __m256i, __mmask16, __m256h, 8)
test_2 (_mm256_maskz_cvt_roundph_epi16, __m256i, __mmask16, __m256h, 8)
test_2 (_mm256_maskz_cvt_roundps_pd, __m256d, __mmask8, __m128, 8)
test_2 (_mm256_maskz_cvtx_roundps_ph, __m128h, __mmask8, __m256, 8)
+test_2 (_mm256_maskz_cvt_roundps_epi32, __m256i, __mmask8, __m256, 9)
+test_2 (_mm256_maskz_cvt_roundps_epu32, __m256i, __mmask8, __m256, 9)
+test_2 (_mm256_maskz_cvt_roundps_epi64, __m256i, __mmask8, __m128, 8)
+test_2 (_mm256_maskz_cvt_roundps_epu64, __m256i, __mmask8, __m128, 8)
test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8)
test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8)
test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8)
@@ -1086,6 +1094,10 @@ test_3 (_mm256_mask_cvt_roundph_epu16, __m256i, __m256i, __mmask16, __m256h, 8)
test_3 (_mm256_mask_cvt_roundph_epi16, __m256i, __m256i, __mmask16, __m256h, 8)
test_3 (_mm256_mask_cvt_roundps_pd, __m256d, __m256d, __mmask8, __m128, 8)
test_3 (_mm256_mask_cvtx_roundps_ph, __m128h, __m128h, __mmask8, __m256, 8)
+test_3 (_mm256_mask_cvt_roundps_epi32, __m256i, __m256i, __mmask8, __m256, 9)
+test_3 (_mm256_mask_cvt_roundps_epu32, __m256i, __m256i, __mmask8, __m256, 9)
+test_3 (_mm256_mask_cvt_roundps_epi64, __m256i, __m256i, __mmask8, __m128, 8)
+test_3 (_mm256_mask_cvt_roundps_epu64, __m256i, __m256i, __mmask8, __m128, 8)
test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
index f51345476d35..593dff8381fa 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -1081,6 +1081,10 @@ test_1 (_mm256_cvt_roundph_epu16, __m256i, __m256h, 8)
test_1 (_mm256_cvt_roundph_epi16, __m256i, __m256h, 8)
test_1 (_mm256_cvt_roundps_pd, __m256d, __m128, 8)
test_1 (_mm256_cvtx_roundps_ph, __m128h, __m256, 8)
+test_1 (_mm256_cvt_roundps_epi32, __m256i, __m256, 9)
+test_1 (_mm256_cvt_roundps_epu32, __m256i, __m256, 9)
+test_1 (_mm256_cvt_roundps_epi64, __m256i, __m128, 8)
+test_1 (_mm256_cvt_roundps_epu64, __m256i, __m128, 8)
test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9)
test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8)
test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9)
@@ -1103,6 +1107,10 @@ test_2 (_mm256_maskz_cvt_roundph_epu16, __m256i, __mmask16, __m256h, 8)
test_2 (_mm256_maskz_cvt_roundph_epi16, __m256i, __mmask16, __m256h, 8)
test_2 (_mm256_maskz_cvt_roundps_pd, __m256d, __mmask8, __m128, 8)
test_2 (_mm256_maskz_cvtx_roundps_ph, __m128h, __mmask8, __m256, 8)
+test_2 (_mm256_maskz_cvt_roundps_epi32, __m256i, __mmask8, __m256, 9)
+test_2 (_mm256_maskz_cvt_roundps_epu32, __m256i, __mmask8, __m256, 9)
+test_2 (_mm256_maskz_cvt_roundps_epi64, __m256i, __mmask8, __m128, 8)
+test_2 (_mm256_maskz_cvt_roundps_epu64, __m256i, __mmask8, __m128, 8)
test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8)
test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8)
test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8)
@@ -1128,6 +1136,10 @@ test_3 (_mm256_mask_cvt_roundph_epu16, __m256i, __m256i, __mmask16, __m256h, 8)
test_3 (_mm256_mask_cvt_roundph_epi16, __m256i, __m256i, __mmask16, __m256h, 8)
test_3 (_mm256_mask_cvt_roundps_pd, __m256d, __m256d, __mmask8, __m128, 8)
test_3 (_mm256_mask_cvtx_roundps_ph, __m128h, __m128h, __mmask8, __m256, 8)
+test_3 (_mm256_mask_cvt_roundps_epi32, __m256i, __m256i, __mmask8, __m256, 9)
+test_3 (_mm256_mask_cvt_roundps_epu32, __m256i, __m256i, __mmask8, __m256, 9)
+test_3 (_mm256_mask_cvt_roundps_epi64, __m256i, __m256i, __mmask8, __m128, 8)
+test_3 (_mm256_mask_cvt_roundps_epu64, __m256i, __m256i, __mmask8, __m128, 8)
test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index 93a0904ba288..d31fec9f2fbb 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -850,6 +850,10 @@
#define __builtin_ia32_vcvtph2w256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2w256_mask_round(A, B, C, 8)
#define __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, 8)
#define __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, 8)
+#define __builtin_ia32_vcvtps2dq256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2dq256_mask_round(A, B, C, 8)
+#define __builtin_ia32_cvtps2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2qq256_mask_round(A, B, C, 8)
+#define __builtin_ia32_cvtps2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2udq256_mask_round(A, B, C, 8)
+#define __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtps2uqq256_mask_round(A, B, C, 8)
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512")
--
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