From 13ea4a6e830da1f245136601e636dec62e74d1a7 Mon Sep 17 00:00:00 2001
From: Jakub Jelinek <jakub@redhat.com>
Date: Mon, 13 Jun 2022 10:53:33 +0200
Subject: [PATCH] i386: Fix up *<dwi>3_doubleword_mask [PR105911]
Another regression caused by my recent patch.
This time because define_insn_and_split only requires that the
constant mask is const_int_operand. When it was only SImode,
that wasn't a problem, HImode neither, but for DImode if we need
to and the shift count we might run into a problem that it isn't
a representable signed 32-bit immediate.
But, we don't really care about the upper bits of the mask, so
we can just mask the CONST_INT with the mode mask.
2022-06-13 Jakub Jelinek <jakub@redhat.com>
PR target/105911
* config/i386/i386.md (*ashl<dwi>3_doubleword_mask,
*<insn><dwi>3_doubleword_mask): Use operands[3] masked with
(<MODE_SIZE> * BITS_PER_UNIT) - 1 as AND operand instead of
operands[3] unmodified.
* gcc.dg/pr105911.c: New test.
---
gcc/config/i386/i386.md | 6 ++++--
gcc/testsuite/gcc.dg/pr105911.c | 16 ++++++++++++++++
2 files changed, 20 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/pr105911.c
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 5b538413942c..3093cb513b98 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -11937,7 +11937,8 @@
rtx xops[3];
xops[0] = gen_reg_rtx (GET_MODE (operands[2]));
xops[1] = operands[2];
- xops[2] = operands[3];
+ xops[2] = GEN_INT (INTVAL (operands[3])
+ & ((<MODE_SIZE> * BITS_PER_UNIT) - 1));
ix86_expand_binary_operator (AND, GET_MODE (operands[2]), xops);
operands[2] = xops[0];
}
@@ -12905,7 +12906,8 @@
rtx xops[3];
xops[0] = gen_reg_rtx (GET_MODE (operands[2]));
xops[1] = operands[2];
- xops[2] = operands[3];
+ xops[2] = GEN_INT (INTVAL (operands[3])
+ & ((<MODE_SIZE> * BITS_PER_UNIT) - 1));
ix86_expand_binary_operator (AND, GET_MODE (operands[2]), xops);
operands[2] = xops[0];
}
diff --git a/gcc/testsuite/gcc.dg/pr105911.c b/gcc/testsuite/gcc.dg/pr105911.c
new file mode 100644
index 000000000000..55df3f15affb
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr105911.c
@@ -0,0 +1,16 @@
+/* PR target/105911 */
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2" } */
+
+__int128 v, x;
+unsigned __int128 w;
+
+void bar (__int128, __int128);
+
+void
+foo (void)
+{
+ bar (v /= v, v >> (v &= 0x100000001));
+ bar (w /= w, w >> (w &= 0x300000003));
+ bar (x /= x, x << (x &= 0x700000007));
+}
--
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