diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 251de55c578c01a66b1439fdcc98d5db3f8846bd..11aae83764ec398922b63869995cc051d1a81803 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,26 @@
+2013-06-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/arm/predicates.md (arm_cond_move_operator): New predicate.
+ * config/arm/arm.md (movsfcc): Use arm_cond_move_operator predicate.
+ (movdfcc): Likewise.
+ * config/arm/vfp.md (*thumb2_movsf_vfp):
+ Disable predication for arm_restrict_it.
+ (*thumb2_movsfcc_vfp): Disable for arm_restrict_it.
+ (*thumb2_movdfcc_vfp): Likewise.
+ (*abssf2_vfp, *absdf2_vfp, *negsf2_vfp, *negdf2_vfp,*addsf3_vfp,
+ *adddf3_vfp, *subsf3_vfp, *subdf3_vfpc, *divsf3_vfp,*divdf3_vfp,
+ *mulsf3_vfp, *muldf3_vfp, *mulsf3negsf_vfp, *muldf3negdf_vfp,
+ *mulsf3addsf_vfp, *muldf3adddf_vfp, *mulsf3subsf_vfp,
+ *muldf3subdf_vfp, *mulsf3negsfaddsf_vfp, *fmuldf3negdfadddf_vfp,
+ *mulsf3negsfsubsf_vfp, *muldf3negdfsubdf_vfp, *fma<SDF:mode>4,
+ *fmsub<SDF:mode>4, *fnmsub<SDF:mode>4, *fnmadd<SDF:mode>4,
+ *extendsfdf2_vfp, *truncdfsf2_vfp, *extendhfsf2, *truncsfhf2,
+ *truncsisf2_vfp, *truncsidf2_vfp, fixuns_truncsfsi2, fixuns_truncdfsi2,
+ *floatsisf2_vfp, *floatsidf2_vfp, floatunssisf2, floatunssidf2,
+ *sqrtsf2_vfp, *sqrtdf2_vfp, *cmpsf_vfp, *cmpsf_trap_vfp, *cmpdf_vfp,
+ *cmpdf_trap_vfp, <vrint_pattern><SDF:mode>2):
+ Disable predication for arm_restrict_it.
+
2013-06-28 Kirill Yukhin <kirill.yukhin@intel.com>
* config/i386/bmiintrin.h (_bextr_u32): New.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index a342c5ef9b9943ea84b587956d8f43889883eb03..0bc22a3f9cb937c60e099632486bf155206389e6 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8851,7 +8851,7 @@
(define_expand "movsfcc"
[(set (match_operand:SF 0 "s_register_operand" "")
- (if_then_else:SF (match_operand 1 "expandable_comparison_operator" "")
+ (if_then_else:SF (match_operand 1 "arm_cond_move_operator" "")
(match_operand:SF 2 "s_register_operand" "")
(match_operand:SF 3 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
@@ -8873,7 +8873,7 @@
(define_expand "movdfcc"
[(set (match_operand:DF 0 "s_register_operand" "")
- (if_then_else:DF (match_operand 1 "expandable_comparison_operator" "")
+ (if_then_else:DF (match_operand 1 "arm_cond_move_operator" "")
(match_operand:DF 2 "s_register_operand" "")
(match_operand:DF 3 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 06c15e29825f4de16a5478eba4ee6a7d67c593da..f4a4515fa3991fe20dc4465052e093934b1f17a8 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -321,6 +321,12 @@
|| maybe_get_arm_condition_code (op) == ARM_NE
|| maybe_get_arm_condition_code (op) == ARM_VC")))
+(define_special_predicate "arm_cond_move_operator"
+ (if_then_else (match_test "arm_restrict_it")
+ (and (match_test "TARGET_FPU_ARMV8")
+ (match_operand 0 "arm_vsel_comparison_operator"))
+ (match_operand 0 "expandable_comparison_operator")))
+
(define_special_predicate "noov_comparison_operator"
(match_code "lt,ge,eq,ne"))
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 918db1758b551c9c7a108718a1a3871d796d64d9..95057e7155fda4d51ec6e3311847e1cfd199e6c1 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -387,6 +387,7 @@
}
"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type"
"r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
(set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
@@ -395,7 +396,6 @@
(set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
)
-
;; DFmode moves
(define_insn "*movdf_vfp"
@@ -525,7 +525,7 @@
[(match_operand 4 "cc_register" "") (const_int 0)])
(match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
(match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it"
"@
it\\t%D3\;fcpys%D3\\t%0, %2
it\\t%d3\;fcpys%d3\\t%0, %1
@@ -573,7 +573,7 @@
[(match_operand 4 "cc_register" "") (const_int 0)])
(match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
(match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
+ "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && !arm_restrict_it"
"@
it\\t%D3\;fcpyd%D3\\t%P0, %P2
it\\t%d3\;fcpyd%d3\\t%P0, %P1
@@ -599,6 +599,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fabss%?\\t%0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "ffariths")]
)
@@ -608,6 +609,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fabsd%?\\t%P0, %P1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "ffarithd")]
)
@@ -619,6 +621,7 @@
fnegs%?\\t%0, %1
eor%?\\t%0, %1, #-2147483648"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "ffariths")]
)
@@ -664,6 +667,7 @@
}
"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "length" "4,4,8")
(set_attr "type" "ffarithd")]
)
@@ -678,6 +682,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fadds%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fadds")]
)
@@ -688,6 +693,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"faddd%?\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "faddd")]
)
@@ -699,6 +705,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fsubs%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fadds")]
)
@@ -709,6 +716,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fsubd%?\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "faddd")]
)
@@ -722,6 +730,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fdivs%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fdivs")]
)
@@ -732,6 +741,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fdivd%?\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fdivd")]
)
@@ -745,6 +755,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmuls%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
@@ -755,6 +766,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fmuld%?\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
@@ -765,6 +777,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmuls%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
@@ -775,6 +788,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fnmuld%?\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
@@ -790,6 +804,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmacs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
@@ -801,6 +816,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fmacd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
@@ -813,6 +829,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmscs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
@@ -824,6 +841,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fmscd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
@@ -836,6 +854,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmacs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
@@ -847,6 +866,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fnmacd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
@@ -861,6 +881,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmscs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
@@ -873,6 +894,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fnmscd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
@@ -886,6 +908,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
@@ -898,6 +921,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
@@ -909,6 +933,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
@@ -921,6 +946,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
@@ -933,6 +959,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fcvtds%?\\t%P0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -942,6 +969,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fcvtsd%?\\t%0, %P1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -951,6 +979,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
"vcvtb%?.f32.f16\\t%0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -960,6 +989,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
"vcvtb%?.f16.f32\\t%0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -969,6 +999,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"ftosizs%?\\t%0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -978,6 +1009,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"ftosizd%?\\t%0, %P1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -988,6 +1020,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"ftouizs%?\\t%0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -997,6 +1030,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"ftouizd%?\\t%0, %P1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1007,6 +1041,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fsitos%?\\t%0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1016,6 +1051,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fsitod%?\\t%P0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1026,6 +1062,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fuitos%?\\t%0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1035,6 +1072,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fuitod%?\\t%P0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1047,6 +1085,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fsqrts%?\\t%0, %1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fdivs")]
)
@@ -1056,6 +1095,7 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"fsqrtd%?\\t%P0, %P1"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fdivd")]
)
@@ -1143,6 +1183,7 @@
fcmps%?\\t%0, %1
fcmpzs%?\\t%0"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmps")]
)
@@ -1155,6 +1196,7 @@
fcmpes%?\\t%0, %1
fcmpezs%?\\t%0"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmps")]
)
@@ -1167,6 +1209,7 @@
fcmpd%?\\t%P0, %P1
fcmpzd%?\\t%P0"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmpd")]
)
@@ -1179,6 +1222,7 @@
fcmped%?\\t%P0, %P1
fcmpezd%?\\t%P0"
[(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmpd")]
)
@@ -1238,6 +1282,7 @@
"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
"vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
[(set_attr "predicable" "<vrint_predicable>")
+ (set_attr "predicable_short_it" "no")
(set_attr "type" "f_rint<vfp_type>")]
)