diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 3fa25a6404de4725e0be527873d23a20634f197d..8466b5d019eaf892b124c9b9fa952eb9ac0356a6 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -560,7 +560,11 @@ source_equal_p (insn_info *insn1, insn_info *insn2)
 
   rtx note1 = find_reg_equal_equiv_note (rinsn1);
   rtx note2 = find_reg_equal_equiv_note (rinsn2);
-  if (note1 && note2 && rtx_equal_p (note1, note2))
+  /* We could handle the case of similar-looking REG_EQUALs as well but
+     would need to verify that no insn in between modifies any of the source
+     operands.  */
+  if (note1 && note2 && rtx_equal_p (note1, note2)
+      && REG_NOTE_KIND (note1) == REG_EQUIV)
     return true;
   return false;
 }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
new file mode 100644
index 0000000000000000000000000000000000000000..15178a2c848e7c1872d715555b1ad2ebb215c030
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } *.
+/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include <stdint-gcc.h>
+
+void __attribute__ ((noipa))
+test (uint16_t *__restrict f, uint32_t *__restrict d, uint64_t *__restrict e,
+      uint16_t x, uint16_t x2, uint16_t x3, uint16_t x4, uint32_t y,
+      uint32_t y2, uint64_t z, int n)
+{
+  for (int i = 0; i < n; ++i)
+    {
+      f[i * 4 + 0] = x;
+      f[i * 4 + 1] = x2;
+      f[i * 4 + 2] = x3;
+      f[i * 4 + 3] = x4;
+      d[i * 2 + 0] = y;
+      d[i * 2 + 1] = y2;
+      e[i] = z;
+    }
+}
+
+/* { dg-final { scan-assembler-times "vsetvli\tzero,\s*\[a-z0-9\]+,\s*e16,\s*m1,\s*ta,\s*ma" 4 } } */