diff --git a/gcc/config/s390/s390-builtin-types.def b/gcc/config/s390/s390-builtin-types.def
index 6f903deb74509ee1df326acfdd0b931659bdeeac..7aeea343126abe50dff7a11df1105b8a3763692a 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -202,9 +202,12 @@ DEF_FN_TYPE_1 (BT_FN_VOID_UINT, BT_VOID, BT_UINT)
DEF_FN_TYPE_2 (BT_FN_DBL_V2DF_INT, BT_DBL, BT_V2DF, BT_INT)
DEF_FN_TYPE_2 (BT_FN_FLT_V4SF_INT, BT_FLT, BT_V4SF, BT_INT)
DEF_FN_TYPE_2 (BT_FN_INT128_INT128_INT128, BT_INT128, BT_INT128, BT_INT128)
+DEF_FN_TYPE_2 (BT_FN_INT128_UINT128_UINT128, BT_INT128, BT_UINT128, BT_UINT128)
DEF_FN_TYPE_2 (BT_FN_INT128_V2DI_V2DI, BT_INT128, BT_V2DI, BT_V2DI)
+DEF_FN_TYPE_2 (BT_FN_INT_INT128_INT128, BT_INT, BT_INT128, BT_INT128)
DEF_FN_TYPE_2 (BT_FN_INT_OV4SI_INT, BT_INT, BT_OV4SI, BT_INT)
DEF_FN_TYPE_2 (BT_FN_INT_OV4SI_OV4SI, BT_INT, BT_OV4SI, BT_OV4SI)
+DEF_FN_TYPE_2 (BT_FN_INT_UINT128_UINT128, BT_INT, BT_UINT128, BT_UINT128)
DEF_FN_TYPE_2 (BT_FN_INT_UV16QI_UV16QI, BT_INT, BT_UV16QI, BT_UV16QI)
DEF_FN_TYPE_2 (BT_FN_INT_UV2DI_UV2DI, BT_INT, BT_UV2DI, BT_UV2DI)
DEF_FN_TYPE_2 (BT_FN_INT_UV4SI_UV4SI, BT_INT, BT_UV4SI, BT_UV4SI)
@@ -304,6 +307,8 @@ DEF_FN_TYPE_2 (BT_FN_VOID_V2DF_FLTPTR, BT_VOID, BT_V2DF, BT_FLTPTR)
DEF_FN_TYPE_3 (BT_FN_BV2DI_V2DF_USHORT_INTPTR, BT_BV2DI, BT_V2DF, BT_USHORT, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_BV4SI_V4SF_USHORT_INTPTR, BT_BV4SI, BT_V4SF, BT_USHORT, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_INT128_INT128_INT128_INT128, BT_INT128, BT_INT128, BT_INT128, BT_INT128)
+DEF_FN_TYPE_3 (BT_FN_INT128_INT128_INT128_INTPTR, BT_INT128, BT_INT128, BT_INT128, BT_INTPTR)
+DEF_FN_TYPE_3 (BT_FN_INT128_UINT128_UINT128_INTPTR, BT_INT128, BT_UINT128, BT_UINT128, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_INT128_V2DI_V2DI_INT128, BT_INT128, BT_V2DI, BT_V2DI, BT_INT128)
DEF_FN_TYPE_3 (BT_FN_INT_OV4SI_OV4SI_INTPTR, BT_INT, BT_OV4SI, BT_OV4SI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_OV4SI_INT_OV4SI_INT, BT_OV4SI, BT_INT, BT_OV4SI, BT_INT)
@@ -433,6 +438,8 @@ DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_UV16QI, BT_BV1TI, BT_BV1TI, BT_BV1TI, BT_UV
DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_UV1TI, BT_BV1TI, BT_BV1TI, BT_BV1TI, BT_UV1TI)
DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_V1TI, BT_BV1TI, BT_BV1TI, BT_BV1TI, BT_V1TI)
DEF_OV_TYPE (BT_OV_BV1TI_BV2DI, BT_BV1TI, BT_BV2DI)
+DEF_OV_TYPE (BT_OV_BV1TI_UV1TI_UV1TI, BT_BV1TI, BT_UV1TI, BT_UV1TI)
+DEF_OV_TYPE (BT_OV_BV1TI_V1TI_V1TI, BT_BV1TI, BT_V1TI, BT_V1TI)
DEF_OV_TYPE (BT_OV_BV2DI_BV1TI_BV1TI, BT_BV2DI, BT_BV1TI, BT_BV1TI)
DEF_OV_TYPE (BT_OV_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI)
DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI)
@@ -505,6 +512,7 @@ DEF_OV_TYPE (BT_OV_FLT_V4SF_INT, BT_FLT, BT_V4SF, BT_INT)
DEF_OV_TYPE (BT_OV_INT_BV16QI_BV16QI, BT_INT, BT_BV16QI, BT_BV16QI)
DEF_OV_TYPE (BT_OV_INT_BV16QI_UV16QI, BT_INT, BT_BV16QI, BT_UV16QI)
DEF_OV_TYPE (BT_OV_INT_BV16QI_V16QI, BT_INT, BT_BV16QI, BT_V16QI)
+DEF_OV_TYPE (BT_OV_INT_BV1TI_BV1TI, BT_INT, BT_BV1TI, BT_BV1TI)
DEF_OV_TYPE (BT_OV_INT_BV2DI_BV2DI, BT_INT, BT_BV2DI, BT_BV2DI)
DEF_OV_TYPE (BT_OV_INT_BV2DI_UV2DI, BT_INT, BT_BV2DI, BT_UV2DI)
DEF_OV_TYPE (BT_OV_INT_BV2DI_V2DI, BT_INT, BT_BV2DI, BT_V2DI)
@@ -527,6 +535,7 @@ DEF_OV_TYPE (BT_OV_INT_V16QI_BV16QI, BT_INT, BT_V16QI, BT_BV16QI)
DEF_OV_TYPE (BT_OV_INT_V16QI_UV16QI, BT_INT, BT_V16QI, BT_UV16QI)
DEF_OV_TYPE (BT_OV_INT_V16QI_V16QI, BT_INT, BT_V16QI, BT_V16QI)
DEF_OV_TYPE (BT_OV_INT_V1TI_UV1TI, BT_INT, BT_V1TI, BT_UV1TI)
+DEF_OV_TYPE (BT_OV_INT_V1TI_V1TI, BT_INT, BT_V1TI, BT_V1TI)
DEF_OV_TYPE (BT_OV_INT_V2DF_UV2DI, BT_INT, BT_V2DF, BT_UV2DI)
DEF_OV_TYPE (BT_OV_INT_V2DF_V2DF, BT_INT, BT_V2DF, BT_V2DF)
DEF_OV_TYPE (BT_OV_INT_V2DI_BV2DI, BT_INT, BT_V2DI, BT_BV2DI)
diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def
index 8eb07e6c79d341dc566c5d215ed639a4eb26990e..9c3334453b81af5e4ce926d0fcbefc92a39633e2 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -1007,6 +1007,7 @@ B_DEF (s390_vceqbs, vec_cmpeqv16qi_cc, 0,
B_DEF (s390_vceqhs, vec_cmpeqv8hi_cc, 0, B_VX, 0, BT_FN_V8HI_UV8HI_UV8HI_INTPTR)
B_DEF (s390_vceqfs, vec_cmpeqv4si_cc, 0, B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI_INTPTR)
B_DEF (s390_vceqgs, vec_cmpeqv2di_cc, 0, B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI_INTPTR)
+B_DEF (s390_vceqqs, vec_cmpeqti_cc, 0, B_VXE3, 0, BT_FN_INT128_UINT128_UINT128_INTPTR)
B_DEF (s390_vfcesbs, vec_cmpeqv4sf_cc, 0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF_INTPTR)
B_DEF (s390_vfcedbs, vec_cmpeqv2df_cc, 0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF_INTPTR)
@@ -1018,6 +1019,8 @@ B_DEF (s390_vchfs, vec_cmphv4si_cc, 0,
B_DEF (s390_vchlfs, vec_cmphlv4si_cc, 0, B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI_INTPTR)
B_DEF (s390_vchgs, vec_cmphv2di_cc, 0, B_VX, 0, BT_FN_V2DI_V2DI_V2DI_INTPTR)
B_DEF (s390_vchlgs, vec_cmphlv2di_cc, 0, B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI_INTPTR)
+B_DEF (s390_vchqs, vec_cmphti_cc, 0, B_VXE3, 0, BT_FN_INT128_INT128_INT128_INTPTR)
+B_DEF (s390_vchlqs, vec_cmphlti_cc , 0, B_VXE3, 0, BT_FN_INT128_UINT128_UINT128_INTPTR)
B_DEF (s390_vfchsbs, vec_cmphv4sf_cc, 0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF_INTPTR)
B_DEF (s390_vfchdbs, vec_cmphv2df_cc, 0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF_INTPTR)
@@ -1028,6 +1031,7 @@ B_DEF (vec_all_eqv16qi, vec_all_eqv16qi, 0,
B_DEF (vec_all_eqv8hi, vec_all_eqv8hi, 0, B_INT | B_VX, 0, BT_FN_INT_UV8HI_UV8HI)
B_DEF (vec_all_eqv4si, vec_all_eqv4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_all_eqv2di, vec_all_eqv2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_all_eqti, vec_all_eqti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_all_eqv4sf, vec_all_eqv4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_all_eqv2df, vec_all_eqv2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1035,6 +1039,7 @@ B_DEF (vec_all_nev16qi, vec_all_nev16qi, 0,
B_DEF (vec_all_nev8hi, vec_all_nev8hi, 0, B_INT | B_VX, 0, BT_FN_INT_UV8HI_UV8HI)
B_DEF (vec_all_nev4si, vec_all_nev4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_all_nev2di, vec_all_nev2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_all_neti, vec_all_neti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_all_nev4sf, vec_all_nev4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_all_nev2df, vec_all_nev2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1046,6 +1051,8 @@ B_DEF (vec_all_gev4si, vec_all_gev4si, 0,
B_DEF (vec_all_geuv4si, vec_all_geuv4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_all_gev2di, vec_all_gev2di, 0, B_INT | B_VX, 0, BT_FN_INT_V2DI_V2DI)
B_DEF (vec_all_geuv2di, vec_all_geuv2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_all_geti, vec_all_geti, 0, B_INT | B_VXE3, 0, BT_FN_INT_INT128_INT128)
+B_DEF (vec_all_geuti, vec_all_geuti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_all_gev4sf, vec_all_gev4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_all_gev2df, vec_all_gev2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1057,6 +1064,8 @@ B_DEF (vec_all_gtv4si, vec_all_gtv4si, 0,
B_DEF (vec_all_gtuv4si, vec_all_gtuv4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_all_gtv2di, vec_all_gtv2di, 0, B_INT | B_VX, 0, BT_FN_INT_V2DI_V2DI)
B_DEF (vec_all_gtuv2di, vec_all_gtuv2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_all_gtti, vec_all_gtti, 0, B_INT | B_VXE3, 0, BT_FN_INT_INT128_INT128)
+B_DEF (vec_all_gtuti, vec_all_gtuti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_all_gtv4sf, vec_all_gtv4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_all_gtv2df, vec_all_gtv2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1068,6 +1077,8 @@ B_DEF (vec_all_lev4si, vec_all_lev4si, 0,
B_DEF (vec_all_leuv4si, vec_all_leuv4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_all_lev2di, vec_all_lev2di, 0, B_INT | B_VX, 0, BT_FN_INT_V2DI_V2DI)
B_DEF (vec_all_leuv2di, vec_all_leuv2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_all_leti, vec_all_leti, 0, B_INT | B_VXE3, 0, BT_FN_INT_INT128_INT128)
+B_DEF (vec_all_leuti, vec_all_leuti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_all_lev4sf, vec_all_lev4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_all_lev2df, vec_all_lev2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1079,6 +1090,8 @@ B_DEF (vec_all_ltv4si, vec_all_ltv4si, 0,
B_DEF (vec_all_ltuv4si, vec_all_ltuv4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_all_ltv2di, vec_all_ltv2di, 0, B_INT | B_VX, 0, BT_FN_INT_V2DI_V2DI)
B_DEF (vec_all_ltuv2di, vec_all_ltuv2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_all_ltti, vec_all_ltti, 0, B_INT | B_VXE3, 0, BT_FN_INT_INT128_INT128)
+B_DEF (vec_all_ltuti, vec_all_ltuti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_all_ltv4sf, vec_all_ltv4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_all_ltv2df, vec_all_ltv2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1111,6 +1124,9 @@ OB_DEF_VAR (s390_vec_all_eq_b64_b, vec_all_eqv2di, B_DEP,
OB_DEF_VAR (s390_vec_all_eq_b64_c, vec_all_eqv2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_eq_u64_a, vec_all_eqv2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_eq_u64_b, vec_all_eqv2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_all_eq_s128, vec_all_eqti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_all_eq_b128, vec_all_eqti, B_VXE3, 0, BT_OV_INT_BV1TI_BV1TI)
+OB_DEF_VAR (s390_vec_all_eq_u128, vec_all_eqti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_all_eq_flt, vec_all_eqv4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_all_eq_dbl, vec_all_eqv2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1143,6 +1159,9 @@ OB_DEF_VAR (s390_vec_all_ne_b64_b, vec_all_nev2di, B_DEP,
OB_DEF_VAR (s390_vec_all_ne_b64_c, vec_all_nev2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_ne_u64_a, vec_all_nev2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_ne_u64_b, vec_all_nev2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_all_ne_s128, vec_all_neti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_all_ne_b128, vec_all_neti, B_VXE3, 0, BT_OV_INT_BV1TI_BV1TI)
+OB_DEF_VAR (s390_vec_all_ne_u128, vec_all_neti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_all_ne_flt, vec_all_nev4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_all_ne_dbl, vec_all_nev2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1175,6 +1194,8 @@ OB_DEF_VAR (s390_vec_all_ge_b64_b, vec_all_gev2di, B_DEP,
OB_DEF_VAR (s390_vec_all_ge_b64_c, vec_all_geuv2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_ge_u64_a, vec_all_geuv2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_ge_u64_b, vec_all_geuv2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_all_ge_s128, vec_all_geti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_all_ge_u128, vec_all_geuti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_all_ge_flt, vec_all_gev4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_all_ge_dbl, vec_all_gev2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1207,6 +1228,8 @@ OB_DEF_VAR (s390_vec_all_gt_b64_b, vec_all_gtv2di, B_DEP,
OB_DEF_VAR (s390_vec_all_gt_b64_c, vec_all_gtuv2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_gt_u64_a, vec_all_gtuv2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_gt_u64_b, vec_all_gtuv2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_all_gt_s128, vec_all_gtti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_all_gt_u128, vec_all_gtuti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_all_gt_flt, vec_all_gtv4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_all_gt_dbl, vec_all_gtv2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1239,6 +1262,8 @@ OB_DEF_VAR (s390_vec_all_le_b64_b, vec_all_lev2di, B_DEP,
OB_DEF_VAR (s390_vec_all_le_b64_c, vec_all_leuv2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_le_u64_a, vec_all_leuv2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_le_u64_b, vec_all_leuv2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_all_le_s128, vec_all_leti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_all_le_u128, vec_all_leuti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_all_le_flt, vec_all_lev4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_all_le_dbl, vec_all_lev2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1271,6 +1296,8 @@ OB_DEF_VAR (s390_vec_all_lt_b64_b, vec_all_ltv2di, B_DEP,
OB_DEF_VAR (s390_vec_all_lt_b64_c, vec_all_ltuv2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_lt_u64_a, vec_all_ltuv2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_all_lt_u64_b, vec_all_ltuv2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_all_lt_s128, vec_all_ltti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_all_lt_u128, vec_all_ltuti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_all_lt_flt, vec_all_ltv4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_all_lt_dbl, vec_all_ltv2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1278,6 +1305,7 @@ B_DEF (vec_any_eqv16qi, vec_any_eqv16qi, 0,
B_DEF (vec_any_eqv8hi, vec_any_eqv8hi, 0, B_INT | B_VX, 0, BT_FN_INT_UV8HI_UV8HI)
B_DEF (vec_any_eqv4si, vec_any_eqv4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_any_eqv2di, vec_any_eqv2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_any_eqti, vec_any_eqti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_any_eqv4sf, vec_any_eqv4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_any_eqv2df, vec_any_eqv2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1285,6 +1313,7 @@ B_DEF (vec_any_nev16qi, vec_any_nev16qi, 0,
B_DEF (vec_any_nev8hi, vec_any_nev8hi, 0, B_INT | B_VX, 0, BT_FN_INT_UV8HI_UV8HI)
B_DEF (vec_any_nev4si, vec_any_nev4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_any_nev2di, vec_any_nev2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_any_neti, vec_any_neti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_any_nev4sf, vec_any_nev4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_any_nev2df, vec_any_nev2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1296,6 +1325,8 @@ B_DEF (vec_any_gev4si, vec_any_gev4si, 0,
B_DEF (vec_any_geuv4si, vec_any_geuv4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_any_gev2di, vec_any_gev2di, 0, B_INT | B_VX, 0, BT_FN_INT_V2DI_V2DI)
B_DEF (vec_any_geuv2di, vec_any_geuv2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_any_geti, vec_any_geti, 0, B_INT | B_VXE3, 0, BT_FN_INT_INT128_INT128)
+B_DEF (vec_any_geuti, vec_any_geuti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_any_gev4sf, vec_any_gev4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_any_gev2df, vec_any_gev2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1307,6 +1338,8 @@ B_DEF (vec_any_gtv4si, vec_any_gtv4si, 0,
B_DEF (vec_any_gtuv4si, vec_any_gtuv4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_any_gtv2di, vec_any_gtv2di, 0, B_INT | B_VX, 0, BT_FN_INT_V2DI_V2DI)
B_DEF (vec_any_gtuv2di, vec_any_gtuv2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_any_gtti, vec_any_gtti, 0, B_INT | B_VXE3, 0, BT_FN_INT_INT128_INT128)
+B_DEF (vec_any_gtuti, vec_any_gtuti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_any_gtv4sf, vec_any_gtv4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_any_gtv2df, vec_any_gtv2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1318,6 +1351,8 @@ B_DEF (vec_any_lev4si, vec_any_lev4si, 0,
B_DEF (vec_any_leuv4si, vec_any_leuv4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_any_lev2di, vec_any_lev2di, 0, B_INT | B_VX, 0, BT_FN_INT_V2DI_V2DI)
B_DEF (vec_any_leuv2di, vec_any_leuv2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_any_leti, vec_any_leti, 0, B_INT | B_VXE3, 0, BT_FN_INT_INT128_INT128)
+B_DEF (vec_any_leuti, vec_any_leuti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_any_lev4sf, vec_any_lev4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_any_lev2df, vec_any_lev2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1329,6 +1364,8 @@ B_DEF (vec_any_ltv4si, vec_any_ltv4si, 0,
B_DEF (vec_any_ltuv4si, vec_any_ltuv4si, 0, B_INT | B_VX, 0, BT_FN_INT_UV4SI_UV4SI)
B_DEF (vec_any_ltv2di, vec_any_ltv2di, 0, B_INT | B_VX, 0, BT_FN_INT_V2DI_V2DI)
B_DEF (vec_any_ltuv2di, vec_any_ltuv2di, 0, B_INT | B_VX, 0, BT_FN_INT_UV2DI_UV2DI)
+B_DEF (vec_any_ltti, vec_any_ltti, 0, B_INT | B_VXE3, 0, BT_FN_INT_INT128_INT128)
+B_DEF (vec_any_ltuti, vec_any_ltuti, 0, B_INT | B_VXE3, 0, BT_FN_INT_UINT128_UINT128)
B_DEF (vec_any_ltv4sf, vec_any_ltv4sf, 0, B_INT | B_VXE, 0, BT_FN_INT_V4SF_V4SF)
B_DEF (vec_any_ltv2df, vec_any_ltv2df, 0, B_INT | B_VX, 0, BT_FN_INT_V2DF_V2DF)
@@ -1361,6 +1398,9 @@ OB_DEF_VAR (s390_vec_any_eq_b64_b, vec_any_eqv2di, B_DEP,
OB_DEF_VAR (s390_vec_any_eq_b64_c, vec_any_eqv2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_eq_u64_a, vec_any_eqv2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_eq_u64_b, vec_any_eqv2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_any_eq_s128, vec_any_eqti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_any_eq_b128, vec_any_eqti, B_VXE3, 0, BT_OV_INT_BV1TI_BV1TI)
+OB_DEF_VAR (s390_vec_any_eq_u128, vec_any_eqti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_any_eq_flt, vec_any_eqv4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_any_eq_dbl, vec_any_eqv2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1393,6 +1433,9 @@ OB_DEF_VAR (s390_vec_any_ne_b64_b, vec_any_nev2di, B_DEP,
OB_DEF_VAR (s390_vec_any_ne_b64_c, vec_any_nev2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_ne_u64_a, vec_any_nev2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_ne_u64_b, vec_any_nev2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_any_ne_s128, vec_any_neti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_any_ne_b128, vec_any_neti, B_VXE3, 0, BT_OV_INT_BV1TI_BV1TI)
+OB_DEF_VAR (s390_vec_any_ne_u128, vec_any_neti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_any_ne_flt, vec_any_nev4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_any_ne_dbl, vec_any_nev2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1425,6 +1468,8 @@ OB_DEF_VAR (s390_vec_any_ge_b64_b, vec_any_gev2di, B_DEP,
OB_DEF_VAR (s390_vec_any_ge_b64_c, vec_any_geuv2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_ge_u64_a, vec_any_geuv2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_ge_u64_b, vec_any_geuv2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_any_ge_s128, vec_any_geti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_any_ge_u128, vec_any_geuti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_any_ge_flt, vec_any_gev4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_any_ge_dbl, vec_any_gev2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1457,6 +1502,8 @@ OB_DEF_VAR (s390_vec_any_gt_b64_b, vec_any_gtv2di, B_DEP,
OB_DEF_VAR (s390_vec_any_gt_b64_c, vec_any_gtuv2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_gt_u64_a, vec_any_gtuv2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_gt_u64_b, vec_any_gtuv2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_any_gt_s128, vec_any_gtti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_any_gt_u128, vec_any_gtuti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_any_gt_flt, vec_any_gtv4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_any_gt_dbl, vec_any_gtv2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1489,6 +1536,8 @@ OB_DEF_VAR (s390_vec_any_le_b64_b, vec_any_lev2di, B_DEP,
OB_DEF_VAR (s390_vec_any_le_b64_c, vec_any_leuv2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_le_u64_a, vec_any_leuv2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_le_u64_b, vec_any_leuv2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_any_le_s128, vec_any_leti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_any_le_u128, vec_any_leuti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_any_le_flt, vec_any_lev4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_any_le_dbl, vec_any_lev2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1521,6 +1570,8 @@ OB_DEF_VAR (s390_vec_any_lt_b64_b, vec_any_ltv2di, B_DEP,
OB_DEF_VAR (s390_vec_any_lt_b64_c, vec_any_ltuv2di, B_DEP, 0, BT_OV_INT_BV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_lt_u64_a, vec_any_ltuv2di, 0, 0, BT_OV_INT_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_any_lt_u64_b, vec_any_ltuv2di, B_DEP, 0, BT_OV_INT_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_any_lt_s128, vec_any_ltti, B_VXE3, 0, BT_OV_INT_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_any_lt_u128, vec_any_ltuti, B_VXE3, 0, BT_OV_INT_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_any_lt_flt, vec_any_ltv4sf, B_VXE, 0, BT_OV_INT_V4SF_V4SF)
OB_DEF_VAR (s390_vec_any_lt_dbl, vec_any_ltv2df, 0, 0, BT_OV_INT_V2DF_V2DF)
@@ -1537,6 +1588,9 @@ OB_DEF_VAR (s390_vec_cmpeq_b32, s390_vceqf, 0,
OB_DEF_VAR (s390_vec_cmpeq_s64, s390_vceqg, 0, 0, BT_OV_BV2DI_V2DI_V2DI)
OB_DEF_VAR (s390_vec_cmpeq_u64, s390_vceqg, 0, 0, BT_OV_BV2DI_UV2DI_UV2DI)
OB_DEF_VAR (s390_vec_cmpeq_b64, s390_vceqg, 0, 0, BT_OV_BV2DI_BV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_cmpeq_s128, s390_vceqq, 0, 0, BT_OV_BV1TI_V1TI_V1TI) /* NOGEN */
+OB_DEF_VAR (s390_vec_cmpeq_u128, s390_vceqq, 0, 0, BT_OV_BV1TI_UV1TI_UV1TI) /* NOGEN */
+OB_DEF_VAR (s390_vec_cmpeq_b128, s390_vceqq, 0, 0, BT_OV_BV1TI_BV1TI_BV1TI) /* NOGEN */
OB_DEF_VAR (s390_vec_cmpeq_flt, s390_vfcesb, B_VXE, 0, BT_OV_BV4SI_V4SF_V4SF)
OB_DEF_VAR (s390_vec_cmpeq_dbl, s390_vfcedb, 0, 0, BT_OV_BV2DI_V2DF_V2DF)
@@ -1544,6 +1598,7 @@ B_DEF (s390_vceqb, vec_cmpeqv16qi, 0,
B_DEF (s390_vceqh, vec_cmpeqv8hi, 0, B_VX, 0, BT_FN_V8HI_UV8HI_UV8HI)
B_DEF (s390_vceqf, vec_cmpeqv4si, 0, B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI)
B_DEF (s390_vceqg, vec_cmpeqv2di, 0, B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
+B_DEF (s390_vceqq, vec_cmpeqti, 0, B_VX, 0, BT_FN_INT128_UINT128_UINT128)
B_DEF (s390_vfcesb, vec_cmpeqv4sf, 0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
B_DEF (s390_vfcedb, vec_cmpeqv2df, 0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
@@ -1556,6 +1611,8 @@ OB_DEF_VAR (s390_vec_cmpge_s32, vec_cmpgev4si, 0,
OB_DEF_VAR (s390_vec_cmpge_u32, vec_cmpgeuv4si, 0, 0, BT_OV_BV4SI_UV4SI_UV4SI)
OB_DEF_VAR (s390_vec_cmpge_s64, vec_cmpgev2di, 0, 0, BT_OV_BV2DI_V2DI_V2DI)
OB_DEF_VAR (s390_vec_cmpge_u64, vec_cmpgeuv2di, 0, 0, BT_OV_BV2DI_UV2DI_UV2DI)
+OB_DEF_VAR (s390_vec_cmpge_s128, vec_cmpgeti, 0, 0, BT_OV_BV1TI_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_cmpge_u128, vec_cmpgeuti, 0, 0, BT_OV_BV1TI_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_cmpge_flt, s390_vfchesb, B_VXE, 0, BT_OV_BV4SI_V4SF_V4SF)
OB_DEF_VAR (s390_vec_cmpge_dbl, s390_vfchedb, 0, 0, BT_OV_BV2DI_V2DF_V2DF)
@@ -1567,6 +1624,8 @@ B_DEF (vec_cmpgev4si, vec_cmpgev4si, 0,
B_DEF (vec_cmpgeuv4si, vec_cmpgeuv4si, 0, B_INT | B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI)
B_DEF (vec_cmpgev2di, vec_cmpgev2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
B_DEF (vec_cmpgeuv2di, vec_cmpgeuv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
+B_DEF (vec_cmpgeti, vec_cmpgeti, 0, B_INT | B_VX, 0, BT_FN_INT128_UINT128_UINT128)
+B_DEF (vec_cmpgeuti, vec_cmpgeuti, 0, B_INT | B_VX, 0, BT_FN_INT128_UINT128_UINT128)
B_DEF (s390_vfchesb, vec_cmpgev4sf_quiet_nocc,0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
B_DEF (s390_vfchedb, vec_cmpgev2df_quiet_nocc,0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
@@ -1579,6 +1638,8 @@ OB_DEF_VAR (s390_vec_cmpgt_s32, s390_vchf, 0,
OB_DEF_VAR (s390_vec_cmpgt_u32, s390_vchlf, 0, 0, BT_OV_BV4SI_UV4SI_UV4SI)
OB_DEF_VAR (s390_vec_cmpgt_s64, s390_vchg, 0, 0, BT_OV_BV2DI_V2DI_V2DI)
OB_DEF_VAR (s390_vec_cmpgt_u64, s390_vchlg, 0, 0, BT_OV_BV2DI_UV2DI_UV2DI)
+OB_DEF_VAR (s390_vec_cmpgt_s128, s390_vchq, 0, 0, BT_OV_BV1TI_V1TI_V1TI) /* NOGEN */
+OB_DEF_VAR (s390_vec_cmpgt_u128, s390_vchlq, 0, 0, BT_OV_BV1TI_UV1TI_UV1TI) /* NOGEN */
OB_DEF_VAR (s390_vec_cmpgt_flt, s390_vfchsb, B_VXE, 0, BT_OV_BV4SI_V4SF_V4SF)
OB_DEF_VAR (s390_vec_cmpgt_dbl, s390_vfchdb, 0, 0, BT_OV_BV2DI_V2DF_V2DF)
@@ -1590,6 +1651,8 @@ B_DEF (s390_vchf, vec_cmpgtv4si, 0,
B_DEF (s390_vchlf, vec_cmpgtuv4si, 0, B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI)
B_DEF (s390_vchg, vec_cmpgtv2di, 0, B_VX, 0, BT_FN_V2DI_V2DI_V2DI)
B_DEF (s390_vchlg, vec_cmpgtuv2di, 0, B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
+B_DEF (s390_vchq, vec_cmpgtti, 0, B_VX, 0, BT_FN_INT128_INT128_INT128)
+B_DEF (s390_vchlq, vec_cmpgtuti, 0, B_VX, 0, BT_FN_INT128_UINT128_UINT128)
B_DEF (s390_vfchsb, vec_cmpgtv4sf_quiet_nocc,0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
B_DEF (s390_vfchdb, vec_cmpgtv2df_quiet_nocc,0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
@@ -1602,6 +1665,8 @@ OB_DEF_VAR (s390_vec_cmple_s32, vec_cmplev4si, 0,
OB_DEF_VAR (s390_vec_cmple_u32, vec_cmpleuv4si, 0, 0, BT_OV_BV4SI_UV4SI_UV4SI)
OB_DEF_VAR (s390_vec_cmple_s64, vec_cmplev2di, 0, 0, BT_OV_BV2DI_V2DI_V2DI)
OB_DEF_VAR (s390_vec_cmple_u64, vec_cmpleuv2di, 0, 0, BT_OV_BV2DI_UV2DI_UV2DI)
+OB_DEF_VAR (s390_vec_cmple_s128, vec_cmpleti, 0, 0, BT_OV_BV1TI_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_cmple_u128, vec_cmpleuti, 0, 0, BT_OV_BV1TI_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_cmple_flt, vec_cmplev4sf, B_VXE, 0, BT_OV_BV4SI_V4SF_V4SF)
OB_DEF_VAR (s390_vec_cmple_dbl, vec_cmplev2df, 0, 0, BT_OV_BV2DI_V2DF_V2DF)
@@ -1613,6 +1678,8 @@ B_DEF (vec_cmplev4si, vec_cmplev4si, 0,
B_DEF (vec_cmpleuv4si, vec_cmpleuv4si, 0, B_INT | B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI)
B_DEF (vec_cmplev2di, vec_cmplev2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
B_DEF (vec_cmpleuv2di, vec_cmpleuv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
+B_DEF (vec_cmpleti, vec_cmpleti, 0, B_INT | B_VX, 0, BT_FN_INT128_UINT128_UINT128)
+B_DEF (vec_cmpleuti, vec_cmpleuti, 0, B_INT | B_VX, 0, BT_FN_INT128_UINT128_UINT128)
B_DEF (vec_cmplev4sf, vec_cmplev4sf_quiet_nocc,0, B_INT | B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
B_DEF (vec_cmplev2df, vec_cmplev2df_quiet_nocc,0, B_INT | B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
@@ -1625,6 +1692,8 @@ OB_DEF_VAR (s390_vec_cmplt_s32, vec_cmpltv4si, 0,
OB_DEF_VAR (s390_vec_cmplt_u32, vec_cmpltuv4si, 0, 0, BT_OV_BV4SI_UV4SI_UV4SI)
OB_DEF_VAR (s390_vec_cmplt_s64, vec_cmpltv2di, 0, 0, BT_OV_BV2DI_V2DI_V2DI)
OB_DEF_VAR (s390_vec_cmplt_u64, vec_cmpltuv2di, 0, 0, BT_OV_BV2DI_UV2DI_UV2DI)
+OB_DEF_VAR (s390_vec_cmplt_s128, vec_cmpltti, 0, 0, BT_OV_BV1TI_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_cmplt_u128, vec_cmpltuti, 0, 0, BT_OV_BV1TI_UV1TI_UV1TI)
OB_DEF_VAR (s390_vec_cmplt_flt, vec_cmpltv4sf, B_VXE, 0, BT_OV_BV4SI_V4SF_V4SF)
OB_DEF_VAR (s390_vec_cmplt_dbl, vec_cmpltv2df, 0, 0, BT_OV_BV2DI_V2DF_V2DF)
@@ -1636,6 +1705,8 @@ B_DEF (vec_cmpltv4si, vec_cmpltv4si, 0,
B_DEF (vec_cmpltuv4si, vec_cmpltuv4si, 0, B_INT | B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI)
B_DEF (vec_cmpltv2di, vec_cmpltv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
B_DEF (vec_cmpltuv2di, vec_cmpltuv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
+B_DEF (vec_cmpltti, vec_cmpltti, 0, B_INT | B_VX, 0, BT_FN_INT128_UINT128_UINT128)
+B_DEF (vec_cmpltuti, vec_cmpltuti, 0, B_INT | B_VX, 0, BT_FN_INT128_UINT128_UINT128)
B_DEF (vec_cmpltv4sf, vec_cmpltv4sf_quiet_nocc,0, B_INT | B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
B_DEF (vec_cmpltv2df, vec_cmpltv2df_quiet_nocc,0, B_INT | B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index f3b0061ac38dd70d52b9dc7bacd2b3041806eb07..313f968c87e7e5aa2739df7504e05f99ffd41b26 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -7296,7 +7296,8 @@ s390_expand_vec_compare_cc (rtx target, enum rtx_code code,
rtx tmp_reg = gen_reg_rtx (SImode);
bool swap_p = false;
- if (GET_MODE_CLASS (GET_MODE (cmp1)) == MODE_VECTOR_INT)
+ if (GET_MODE_CLASS (GET_MODE (cmp1)) == MODE_VECTOR_INT
+ || GET_MODE (cmp1) == TImode)
{
switch (code)
{
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 606c6826860694a7642cae25b5883348773d80b6..57a9d20f7f7646ffaddcc8cb4ac9aed9e5051cc7 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -66,6 +66,7 @@
; All integer vector modes supported in a vector register + TImode
(define_mode_iterator VIT [V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1TI TI])
+(define_mode_iterator VIT_VXE3 [V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI (V1TI "TARGET_VXE3") (TI "TARGET_VXE3")])
(define_mode_iterator VI [V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI])
(define_mode_iterator VI_VXE3 [V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI (V2DI "TARGET_VXE3")])
(define_mode_iterator VI_QHS [V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI])
@@ -237,6 +238,7 @@
; Comparison operators on int and fp compares which are directly
; supported by the HW.
(define_code_iterator VICMP_HW_OP [eq gt gtu])
+(define_code_iterator VICMP_HW_OP2 [gt gtu])
; For int insn_cmp_op can be used in the insn name as well as in the asm output.
(define_code_attr insn_cmp_op [(eq "eq") (gt "h") (gtu "hl") (ge "he")])
@@ -1978,8 +1980,8 @@
(define_expand "vec_cmp<mode><tointvec>"
[(set (match_operand:<TOINTVEC> 0 "register_operand" "")
(match_operator:<TOINTVEC> 1 "vcond_comparison_operator"
- [(match_operand:V_HW 2 "register_operand" "")
- (match_operand:V_HW 3 "nonmemory_operand" "")]))]
+ [(match_operand:V_HW1 2 "register_operand" "")
+ (match_operand:V_HW1 3 "nonmemory_operand" "")]))]
"TARGET_VX"
{
s390_expand_vec_compare (operands[0], GET_CODE(operands[1]), operands[2], operands[3]);
@@ -1997,19 +1999,19 @@
DONE;
})
-(define_insn "*vec_cmp<VICMP_HW_OP:code><VI:mode><VI:mode>_nocc"
- [(set (match_operand:VI 2 "register_operand" "=v")
- (VICMP_HW_OP:VI (match_operand:VI 0 "register_operand" "v")
- (match_operand:VI 1 "register_operand" "v")))]
+(define_insn "*vec_cmp<VICMP_HW_OP:code><VIT_VXE3:mode><VIT_VXE3:mode>_nocc"
+ [(set (match_operand:VIT_VXE3 2 "register_operand" "=v")
+ (VICMP_HW_OP:VIT_VXE3 (match_operand:VIT_VXE3 0 "register_operand" "v")
+ (match_operand:VIT_VXE3 1 "register_operand" "v")))]
"TARGET_VX"
- "vc<VICMP_HW_OP:insn_cmp_op><VI:bhfgq>\t%v2,%v0,%v1"
+ "vc<VICMP_HW_OP:insn_cmp_op><VIT_VXE3:bhfgq>\t%v2,%v0,%v1"
[(set_attr "op_type" "VRR")])
(define_insn_and_split "*vec_cmpeq<mode><mode>_nocc_emu"
[(set (match_operand:VI_HW_T 0 "register_operand" "=v")
(eq:VI_HW_T (match_operand:VI_HW_T 1 "register_operand" "v")
(match_operand:VI_HW_T 2 "register_operand" "v")))]
- "TARGET_VX"
+ "TARGET_VX && !TARGET_VXE3"
"#"
"&& can_create_pseudo_p ()"
[(set (match_dup 3)
@@ -2031,7 +2033,7 @@
[(set (match_operand:VI_HW_T 0 "register_operand" "=v")
(gt:VI_HW_T (match_operand:VI_HW_T 1 "register_operand" "v")
(match_operand:VI_HW_T 2 "register_operand" "v")))]
- "TARGET_VX"
+ "TARGET_VX && !TARGET_VXE3"
"#"
"&& can_create_pseudo_p ()"
[(set (match_dup 3)
diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index c332e025b2aeacdaafe58121e577b44ad83fa1e2..a25122db3b28fc5a402ae367de35f8828af23244 100644
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -748,10 +748,10 @@
; vec_all/any int compares
-(define_expand "vec_all_<intcmpcc:code><VI_HW:mode>"
- [(match_operand:SI 0 "register_operand" "")
- (intcmpcc (match_operand:VI_HW 1 "register_operand" "")
- (match_operand:VI_HW 2 "register_operand" ""))]
+(define_expand "vec_all_<intcmpcc:code><VIT_HW_VXE3_T:mode>"
+ [(match_operand:SI 0 "register_operand" "")
+ (intcmpcc (match_operand:VIT_HW_VXE3_T 1 "register_operand" "")
+ (match_operand:VIT_HW_VXE3_T 2 "register_operand" ""))]
"TARGET_VX"
{
s390_expand_vec_compare_cc (operands[0],
@@ -762,10 +762,10 @@
DONE;
})
-(define_expand "vec_any_<intcmpcc:code><VI_HW:mode>"
- [(match_operand:SI 0 "register_operand" "")
- (intcmpcc (match_operand:VI_HW 1 "register_operand" "")
- (match_operand:VI_HW 2 "register_operand" ""))]
+(define_expand "vec_any_<intcmpcc:code><VIT_HW_VXE3_T:mode>"
+ [(match_operand:SI 0 "register_operand" "")
+ (intcmpcc (match_operand:VIT_HW_VXE3_T 1 "register_operand" "")
+ (match_operand:VIT_HW_VXE3_T 2 "register_operand" ""))]
"TARGET_VX"
{
s390_expand_vec_compare_cc (operands[0],
@@ -809,10 +809,10 @@
; Compare without generating CC
-(define_expand "vec_cmp<intcmp:code><VI_HW:mode>"
- [(set (match_operand:VI_HW 0 "register_operand" "=v")
- (intcmp:VI_HW (match_operand:VI_HW 1 "register_operand" "v")
- (match_operand:VI_HW 2 "register_operand" "v")))]
+(define_expand "vec_cmp<intcmp:code><VIT_HW_VXE3_T:mode>"
+ [(set (match_operand:VIT_HW_VXE3_T 0 "register_operand" "=v")
+ (intcmp:VIT_HW_VXE3_T (match_operand:VIT_HW_VXE3_T 1 "register_operand" "v")
+ (match_operand:VIT_HW_VXE3_T 2 "register_operand" "v")))]
"TARGET_VX"
{
s390_expand_vec_compare (operands[0], <intcmp:CODE>, operands[1], operands[2]);
@@ -1979,13 +1979,13 @@
; All comparisons which produce a CC need fully populated (VI_HW)
; vector arguments. Otherwise the any/all CCs would be just bogus.
-(define_insn "*vec_cmp<VICMP:insn_cmp><VI_HW:mode>_cconly"
+(define_insn "*vec_cmp<VICMP:insn_cmp><VIT_HW_VXE3_T:mode>_cconly"
[(set (reg:VICMP CC_REGNUM)
- (compare:VICMP (match_operand:VI_HW 0 "register_operand" "v")
- (match_operand:VI_HW 1 "register_operand" "v")))
- (clobber (match_scratch:VI_HW 2 "=v"))]
+ (compare:VICMP (match_operand:VIT_HW_VXE3_T 0 "register_operand" "v")
+ (match_operand:VIT_HW_VXE3_T 1 "register_operand" "v")))
+ (clobber (match_scratch:VIT_HW_VXE3_T 2 "=v"))]
"TARGET_VX"
- "vc<VICMP:insn_cmp><VI_HW:bhfgq>s\t%v2,%v0,%v1"
+ "vc<VICMP:insn_cmp><VIT_HW_VXE3_T:bhfgq>s\t%v2,%v0,%v1"
[(set_attr "op_type" "VRR")])
; FIXME: The following 2x3 definitions should be merged into 2 with
@@ -1993,68 +1993,68 @@
; operator (eq) depending on the mode CCVEQ (mode_iterator). Or the
; other way around - setting the mode depending on the code
; (code_iterator).
-(define_expand "vec_cmpeq<VI_HW:mode>_cc"
+(define_expand "vec_cmpeq<VIT_HW_VXE3_T:mode>_cc"
[(parallel
[(set (reg:CCVEQ CC_REGNUM)
- (compare:CCVEQ (match_operand:VI_HW 1 "register_operand" "v")
- (match_operand:VI_HW 2 "register_operand" "v")))
- (set (match_operand:VI_HW 0 "register_operand" "=v")
- (eq:VI_HW (match_dup 1) (match_dup 2)))])
+ (compare:CCVEQ (match_operand:VIT_HW_VXE3_T 1 "register_operand" "v")
+ (match_operand:VIT_HW_VXE3_T 2 "register_operand" "v")))
+ (set (match_operand:VIT_HW_VXE3_T 0 "register_operand" "=v")
+ (eq:VIT_HW_VXE3_T (match_dup 1) (match_dup 2)))])
(set (match_operand:SI 3 "memory_operand" "")
(unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))]
"TARGET_VX")
-(define_expand "vec_cmph<VI_HW:mode>_cc"
+(define_expand "vec_cmph<VIT_HW_VXE3_T:mode>_cc"
[(parallel
[(set (reg:CCVIH CC_REGNUM)
- (compare:CCVIH (match_operand:VI_HW 1 "register_operand" "v")
- (match_operand:VI_HW 2 "register_operand" "v")))
- (set (match_operand:VI_HW 0 "register_operand" "=v")
- (gt:VI_HW (match_dup 1) (match_dup 2)))])
+ (compare:CCVIH (match_operand:VIT_HW_VXE3_T 1 "register_operand" "v")
+ (match_operand:VIT_HW_VXE3_T 2 "register_operand" "v")))
+ (set (match_operand:VIT_HW_VXE3_T 0 "register_operand" "=v")
+ (gt:VIT_HW_VXE3_T (match_dup 1) (match_dup 2)))])
(set (match_operand:SI 3 "memory_operand" "")
(unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))]
"TARGET_VX")
-(define_expand "vec_cmphl<VI_HW:mode>_cc"
+(define_expand "vec_cmphl<VIT_HW_VXE3_T:mode>_cc"
[(parallel
[(set (reg:CCVIHU CC_REGNUM)
- (compare:CCVIHU (match_operand:VI_HW 1 "register_operand" "v")
- (match_operand:VI_HW 2 "register_operand" "v")))
- (set (match_operand:VI_HW 0 "register_operand" "=v")
- (gtu:VI_HW (match_dup 1) (match_dup 2)))])
+ (compare:CCVIHU (match_operand:VIT_HW_VXE3_T 1 "register_operand" "v")
+ (match_operand:VIT_HW_VXE3_T 2 "register_operand" "v")))
+ (set (match_operand:VIT_HW_VXE3_T 0 "register_operand" "=v")
+ (gtu:VIT_HW_VXE3_T (match_dup 1) (match_dup 2)))])
(set (match_operand:SI 3 "memory_operand" "")
(unspec:SI [(reg:CCVIHU CC_REGNUM)] UNSPEC_CC_TO_INT))]
"TARGET_VX")
-(define_insn "*vec_cmpeq<VI_HW:mode>_cc"
+(define_insn "*vec_cmpeq<VIT_HW_VXE3_T:mode>_cc"
[(set (reg:CCVEQ CC_REGNUM)
- (compare:CCVEQ (match_operand:VI_HW 0 "register_operand" "v")
- (match_operand:VI_HW 1 "register_operand" "v")))
- (set (match_operand:VI_HW 2 "register_operand" "=v")
- (eq:VI_HW (match_dup 0) (match_dup 1)))]
+ (compare:CCVEQ (match_operand:VIT_HW_VXE3_T 0 "register_operand" "v")
+ (match_operand:VIT_HW_VXE3_T 1 "register_operand" "v")))
+ (set (match_operand:VIT_HW_VXE3_T 2 "register_operand" "=v")
+ (eq:VIT_HW_VXE3_T (match_dup 0) (match_dup 1)))]
"TARGET_VX"
- "vceq<VI_HW:bhfgq>s\t%v2,%v0,%v1"
+ "vceq<VIT_HW_VXE3_T:bhfgq>s\t%v2,%v0,%v1"
[(set_attr "op_type" "VRR")])
-(define_insn "*vec_cmph<VI_HW:mode>_cc"
+(define_insn "*vec_cmph<VIT_HW_VXE3_T:mode>_cc"
[(set (reg:CCVIH CC_REGNUM)
- (compare:CCVIH (match_operand:VI_HW 0 "register_operand" "v")
- (match_operand:VI_HW 1 "register_operand" "v")))
- (set (match_operand:VI_HW 2 "register_operand" "=v")
- (gt:VI_HW (match_dup 0) (match_dup 1)))]
+ (compare:CCVIH (match_operand:VIT_HW_VXE3_T 0 "register_operand" "v")
+ (match_operand:VIT_HW_VXE3_T 1 "register_operand" "v")))
+ (set (match_operand:VIT_HW_VXE3_T 2 "register_operand" "=v")
+ (gt:VIT_HW_VXE3_T (match_dup 0) (match_dup 1)))]
"TARGET_VX"
- "vch<VI_HW:bhfgq>s\t%v2,%v0,%v1"
+ "vch<VIT_HW_VXE3_T:bhfgq>s\t%v2,%v0,%v1"
[(set_attr "op_type" "VRR")])
-(define_insn "*vec_cmphl<VI_HW:mode>_cc"
+(define_insn "*vec_cmphl<VIT_HW_VXE3_T:mode>_cc"
[(set (reg:CCVIHU CC_REGNUM)
- (compare:CCVIHU (match_operand:VI_HW 0 "register_operand" "v")
- (match_operand:VI_HW 1 "register_operand" "v")))
- (set (match_operand:VI_HW 2 "register_operand" "=v")
- (gtu:VI_HW (match_dup 0) (match_dup 1)))]
+ (compare:CCVIHU (match_operand:VIT_HW_VXE3_T 0 "register_operand" "v")
+ (match_operand:VIT_HW_VXE3_T 1 "register_operand" "v")))
+ (set (match_operand:VIT_HW_VXE3_T 2 "register_operand" "=v")
+ (gtu:VIT_HW_VXE3_T (match_dup 0) (match_dup 1)))]
"TARGET_VX"
- "vchl<VI_HW:bhfgq>s\t%v2,%v0,%v1"
+ "vchl<VIT_HW_VXE3_T:bhfgq>s\t%v2,%v0,%v1"
[(set_attr "op_type" "VRR")])
;;