From 3bd11f791e08a5676f176d632c729d147f12dcaa Mon Sep 17 00:00:00 2001
From: Jakub Jelinek <jakub@redhat.com>
Date: Mon, 7 Mar 2022 09:40:51 +0100
Subject: [PATCH] i386: Fix up cond_{and,ior,xor,mul}* [PR104779]
The following testcase ICEs, because the cond_andv* expander
has vector_operand predicates in both of the commutative inputs
and calls gen_andv*_mask which calls ix86_binary_operator_ok
in its condition, but nothing calls ix86_fixup_binary_operands_no_copy
during the expansion, which means cond_* accepts even operands
like 2 MEMs which then can't be matched.
The following patch handles it like most other insns that the other
cond_* patterns use - by having a separate define_expand that calls
ix86_fixup_binary_operands_no_copy and define_ins with
ix86_binary_operator_ok.
2022-03-07 Jakub Jelinek <jakub@redhat.com>
PR target/104779
* config/i386/sse.md (avx512dq_mul<mode>3<mask_name>): New
define_expand pattern. Rename define_insn to ...
(*avx512dq_mul<mode>3<mask_name>): ... this.
(<code><mode>3_mask): New any_logic define_expand pattern.
(<mask_codefor><code><mode>3<mask_name>): Rename to ...
(*<code><mode>3<mask_name>): ... this.
* gcc.target/i386/pr104779.c: New test.
---
gcc/config/i386/sse.md | 23 ++++++++++++++++++--
gcc/testsuite/gcc.target/i386/pr104779.c | 27 ++++++++++++++++++++++++
2 files changed, 48 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr104779.c
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3066ea3734ad..0076475d7ba1 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15210,7 +15210,15 @@
DONE;
})
-(define_insn "avx512dq_mul<mode>3<mask_name>"
+(define_expand "avx512dq_mul<mode>3<mask_name>"
+ [(set (match_operand:VI8_AVX512VL 0 "register_operand")
+ (mult:VI8_AVX512VL
+ (match_operand:VI8_AVX512VL 1 "bcst_vector_operand")
+ (match_operand:VI8_AVX512VL 2 "bcst_vector_operand")))]
+ "TARGET_AVX512DQ && <mask_mode512bit_condition>"
+ "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
+
+(define_insn "*avx512dq_mul<mode>3<mask_name>"
[(set (match_operand:VI8_AVX512VL 0 "register_operand" "=v")
(mult:VI8_AVX512VL
(match_operand:VI8_AVX512VL 1 "bcst_vector_operand" "%v")
@@ -16824,7 +16832,18 @@
DONE;
})
-(define_insn "<mask_codefor><code><mode>3<mask_name>"
+(define_expand "<code><mode>3_mask"
+ [(set (match_operand:VI48_AVX512VL 0 "register_operand")
+ (vec_merge:VI48_AVX512VL
+ (any_logic:VI48_AVX512VL
+ (match_operand:VI48_AVX512VL 1 "bcst_vector_operand")
+ (match_operand:VI48_AVX512VL 2 "bcst_vector_operand"))
+ (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand")
+ (match_operand:<avx512fmaskmode> 4 "register_operand")))]
+ "TARGET_AVX512F"
+ "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
+
+(define_insn "*<code><mode>3<mask_name>"
[(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,x,v")
(any_logic:VI48_AVX_AVX512F
(match_operand:VI48_AVX_AVX512F 1 "bcst_vector_operand" "%0,x,v")
diff --git a/gcc/testsuite/gcc.target/i386/pr104779.c b/gcc/testsuite/gcc.target/i386/pr104779.c
new file mode 100644
index 000000000000..2dd8ec6a1830
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104779.c
@@ -0,0 +1,27 @@
+/* PR target/104779 */
+/* { dg-do compile } */
+/* { dg-options "-O1 --param sccvn-max-alias-queries-per-access=0" } */
+
+__attribute__ ((simd)) int
+foo (int x, int y, int z)
+{
+ return (x & y) * !!z;
+}
+
+__attribute__ ((simd)) int
+bar (int x, int y, int z)
+{
+ return (x | y) * !!z;
+}
+
+__attribute__ ((simd)) int
+baz (int x, int y, int z)
+{
+ return (x ^ y) * !!z;
+}
+
+__attribute__ ((simd, target ("avx512dq"))) long
+qux (long x, long y, long z)
+{
+ return (x * y) * !!z;
+}
--
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