From 3dc0f23ad0c317be6a9448e1ac15c06bc41d5cee Mon Sep 17 00:00:00 2001
From: Uros Bizjak <uros@gcc.gnu.org>
Date: Sat, 29 Dec 2007 16:35:14 +0100
Subject: [PATCH] sse.md ("*divv4sf3"): Rename to "sse_divv4sf3".
* config/i386/sse.md ("*divv4sf3"): Rename to "sse_divv4sf3".
("*sse_rsqrtv4sf2"): Export.
("*sse_sqrtv4sf2"): Ditto.
* config/i386/i386.c (enum ix86_builtins) [IX86_BUILTIN_RSQRTPS_NR,
IX86_BUILTIN_SQRTPS_NR]: New constants.
(struct builtin_description) [IX86_BUILTIN_DIVPS]: Use
CODE_FOR_sse_divv4sf3.
[IX86_BUILTIN_SQRTPS]: Use CODE_FOR_sse_sqrtv4sf2.
[IX86_BUILTIN_SQRTPS_NR]: New.
[IX86_BUILTIN_RSQRTPS_NR]: Ditto.
(ix86_init_mmx_sse_builtins): Initialize __builtin_ia32_rsqrtps_nr and
__builtin_ia32_sqrtps_nr.
(ix86_builtin_vectorized_function): Convert BUILT_IN_SQRTF to
IX86_BUILTIN_SQRTPS_NR.
(ix86_builtin_reciprocal): Convert IX86_BUILTIN_SQRTPS_NR to
IX86_BUILTIN_RSQRTPS_NR.
From-SVN: r131220
---
gcc/ChangeLog | 35 +++++++++++++++++++++++++++--------
gcc/config/i386/i386.c | 16 +++++++++++-----
gcc/config/i386/sse.md | 38 +++++++++++++++++++-------------------
3 files changed, 57 insertions(+), 32 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 63c28d19a89e..2fef7a2816af 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,4 +1,23 @@
-2007-12-08 Brian Dessent <brian@dessent.net>
+2007-12-29 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/sse.md ("*divv4sf3"): Rename to "sse_divv4sf3".
+ ("*sse_rsqrtv4sf2"): Export.
+ ("*sse_sqrtv4sf2"): Ditto.
+ * config/i386/i386.c (enum ix86_builtins) [IX86_BUILTIN_RSQRTPS_NR,
+ IX86_BUILTIN_SQRTPS_NR]: New constants.
+ (struct builtin_description) [IX86_BUILTIN_DIVPS]: Use
+ CODE_FOR_sse_divv4sf3.
+ [IX86_BUILTIN_SQRTPS]: Use CODE_FOR_sse_sqrtv4sf2.
+ [IX86_BUILTIN_SQRTPS_NR]: New.
+ [IX86_BUILTIN_RSQRTPS_NR]: Ditto.
+ (ix86_init_mmx_sse_builtins): Initialize __builtin_ia32_rsqrtps_nr and
+ __builtin_ia32_sqrtps_nr.
+ (ix86_builtin_vectorized_function): Convert BUILT_IN_SQRTF to
+ IX86_BUILTIN_SQRTPS_NR.
+ (ix86_builtin_reciprocal): Convert IX86_BUILTIN_SQRTPS_NR to
+ IX86_BUILTIN_RSQRTPS_NR.
+
+2007-12-27 Brian Dessent <brian@dessent.net>
* doc/invoke.texi (Optimize Options): Add missing opindex for
-fno-toplevel-reorder.
@@ -39,7 +58,8 @@
2007-12-21 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
- * pa.c (hppa_legitimize_address): Use INT14_OK_STRICT in mask selection.
+ * config/pa/pa.c (hppa_legitimize_address): Use INT14_OK_STRICT in
+ mask selection.
PR target/34525
* pa.c (legitimize_pic_address): Emit insn to load function label
@@ -223,12 +243,11 @@
2007-12-18 Razya Ladelsky <razya@il.ibm.com>
- * tree-parloops.c (reduiction_info): Change documentation of
- reduction_initial field.
- (initialize_reductions): Remove creation of reduction_initial
- variable.
- (create_loads_for_reductions): don't join reduction_initial to
- the loaded value.
+ * tree-parloops.c (reduiction_info): Change documentation of
+ reduction_initial field.
+ (initialize_reductions): Remove creation of reduction_initial variable.
+ (create_loads_for_reductions): don't join reduction_initial to
+ the loaded value.
2007-12-18 Kaz Kylheku <kaz@zeugmasystems.com>
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 95a34969cc6c..232d6fe6b608 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -17093,9 +17093,11 @@ enum ix86_builtins
IX86_BUILTIN_RCPPS,
IX86_BUILTIN_RCPSS,
IX86_BUILTIN_RSQRTPS,
+ IX86_BUILTIN_RSQRTPS_NR,
IX86_BUILTIN_RSQRTSS,
IX86_BUILTIN_RSQRTF,
IX86_BUILTIN_SQRTPS,
+ IX86_BUILTIN_SQRTPS_NR,
IX86_BUILTIN_SQRTSS,
IX86_BUILTIN_UNPCKHPS,
@@ -17849,7 +17851,7 @@ static const struct builtin_description bdesc_2arg[] =
{ OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, 0 },
{ OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, 0 },
{ OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, 0 },
- { OPTION_MASK_ISA_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, 0 },
+ { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, 0 },
{ OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, 0 },
{ OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, 0 },
{ OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, 0 },
@@ -18158,8 +18160,10 @@ static const struct builtin_description bdesc_1arg[] =
{ OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, UNKNOWN, 0 },
{ OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, UNKNOWN, 0 },
- { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, UNKNOWN, 0 },
+ { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, UNKNOWN, 0 },
+ { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS_NR, UNKNOWN, 0 },
{ OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, UNKNOWN, 0 },
+ { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, 0 },
{ OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, UNKNOWN, 0 },
{ OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, UNKNOWN, 0 },
@@ -19279,12 +19283,14 @@ ix86_init_mmx_sse_builtins (void)
def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
+ def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtps_nr", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS_NR);
def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
ftype = build_function_type_list (float_type_node,
float_type_node,
NULL_TREE);
def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtf", ftype, IX86_BUILTIN_RSQRTF);
def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
+ def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtps_nr", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS_NR);
def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
@@ -21301,7 +21307,7 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
case BUILT_IN_SQRTF:
if (out_mode == SFmode && out_n == 4
&& in_mode == SFmode && in_n == 4)
- return ix86_builtins[IX86_BUILTIN_SQRTPS];
+ return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
break;
case BUILT_IN_LRINT:
@@ -21463,8 +21469,8 @@ ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
switch (fn)
{
/* Vectorized version of sqrt to rsqrt conversion. */
- case IX86_BUILTIN_SQRTPS:
- return ix86_builtins[IX86_BUILTIN_RSQRTPS];
+ case IX86_BUILTIN_SQRTPS_NR:
+ return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
default:
return NULL_TREE;
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 12fb4a230c9c..3c0d497392e7 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -490,7 +490,7 @@
}
})
-(define_insn "*divv4sf3"
+(define_insn "sse_divv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(div:V4SF (match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
@@ -532,16 +532,7 @@
[(set_attr "type" "sse")
(set_attr "mode" "SF")])
-(define_insn "*sse_rsqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
- "TARGET_SSE"
- "rsqrtps\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "V4SF")])
-
-(define_expand "sse_rsqrtv4sf2"
+(define_expand "rsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF
[(match_operand:V4SF 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
@@ -556,6 +547,15 @@
}
})
+(define_insn "sse_rsqrtv4sf2"
+ [(set (match_operand:V4SF 0 "register_operand" "=x")
+ (unspec:V4SF
+ [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
+ "TARGET_SSE"
+ "rsqrtps\t{%1, %0|%0, %1}"
+ [(set_attr "type" "sse")
+ (set_attr "mode" "V4SF")])
+
(define_insn "sse_vmrsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_merge:V4SF
@@ -568,14 +568,6 @@
[(set_attr "type" "sse")
(set_attr "mode" "SF")])
-(define_insn "*sqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
- "TARGET_SSE"
- "sqrtps\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "V4SF")])
-
(define_expand "sqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=")
(sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
@@ -590,6 +582,14 @@
}
})
+(define_insn "sse_sqrtv4sf2"
+ [(set (match_operand:V4SF 0 "register_operand" "=x")
+ (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
+ "TARGET_SSE"
+ "sqrtps\t{%1, %0|%0, %1}"
+ [(set_attr "type" "sse")
+ (set_attr "mode" "V4SF")])
+
(define_insn "sse_vmsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_merge:V4SF
--
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