diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f9fa30f99a57a10f2394e55e83d8eed8bcdc717e..666b76c4ffdf66e58f493f83c3c303426f161d0e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2004-12-08 Richard Henderson <rth@redhat.com>
+
+ * config/i386/i386.md: Use FLAGS_REG everywhere.
+
2004-12-08 Eric Christopher <echristo@redhat.com>
* config/mips/mips.c (mips_scalar_mode_supported_p): Rewrite
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 84b97e86805ec8976c0499e359ab833d717d6174..0d2ccb2bbb42265a4dc822c800934c3616e58c52 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -511,7 +511,7 @@
})
(define_insn "cmpdi_ccno_1_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
(match_operand:DI 1 "const0_operand" "n,n")))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
@@ -523,7 +523,7 @@
(set_attr "mode" "DI")])
(define_insn "*cmpdi_minus_1_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
(match_operand:DI 1 "x86_64_general_operand" "re,mr"))
(const_int 0)))]
@@ -540,7 +540,7 @@
"")
(define_insn "cmpdi_1_insn_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
(match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
@@ -550,7 +550,7 @@
(define_insn "*cmpsi_ccno_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
(match_operand:SI 1 "const0_operand" "n,n")))]
"ix86_match_ccmode (insn, CCNOmode)"
@@ -562,7 +562,7 @@
(set_attr "mode" "SI")])
(define_insn "*cmpsi_minus_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
(match_operand:SI 1 "general_operand" "ri,mr"))
(const_int 0)))]
@@ -579,7 +579,7 @@
"")
(define_insn "*cmpsi_1_insn"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
(match_operand:SI 1 "general_operand" "ri,mr")))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
@@ -589,7 +589,7 @@
(set_attr "mode" "SI")])
(define_insn "*cmphi_ccno_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
(match_operand:HI 1 "const0_operand" "n,n")))]
"ix86_match_ccmode (insn, CCNOmode)"
@@ -601,7 +601,7 @@
(set_attr "mode" "HI")])
(define_insn "*cmphi_minus_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
(match_operand:HI 1 "general_operand" "ri,mr"))
(const_int 0)))]
@@ -611,7 +611,7 @@
(set_attr "mode" "HI")])
(define_insn "*cmphi_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
(match_operand:HI 1 "general_operand" "ri,mr")))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
@@ -621,7 +621,7 @@
(set_attr "mode" "HI")])
(define_insn "*cmpqi_ccno_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
(match_operand:QI 1 "const0_operand" "n,n")))]
"ix86_match_ccmode (insn, CCNOmode)"
@@ -633,7 +633,7 @@
(set_attr "mode" "QI")])
(define_insn "*cmpqi_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
(match_operand:QI 1 "general_operand" "qi,mq")))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
@@ -643,7 +643,7 @@
(set_attr "mode" "QI")])
(define_insn "*cmpqi_minus_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
(match_operand:QI 1 "general_operand" "qi,mq"))
(const_int 0)))]
@@ -653,7 +653,7 @@
(set_attr "mode" "QI")])
(define_insn "*cmpqi_ext_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(match_operand:QI 0 "general_operand" "Qm")
(subreg:QI
@@ -667,7 +667,7 @@
(set_attr "mode" "QI")])
(define_insn "*cmpqi_ext_1_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(match_operand:QI 0 "register_operand" "Q")
(subreg:QI
@@ -681,7 +681,7 @@
(set_attr "mode" "QI")])
(define_insn "*cmpqi_ext_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(subreg:QI
(zero_extract:SI
@@ -708,7 +708,7 @@
"")
(define_insn "cmpqi_ext_3_insn"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(subreg:QI
(zero_extract:SI
@@ -722,7 +722,7 @@
(set_attr "mode" "QI")])
(define_insn "cmpqi_ext_3_insn_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(subreg:QI
(zero_extract:SI
@@ -736,7 +736,7 @@
(set_attr "mode" "QI")])
(define_insn "*cmpqi_ext_4"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(subreg:QI
(zero_extract:SI
@@ -5301,7 +5301,7 @@
"")
(define_insn "*adddi_2_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "x86_64_general_operand" "rme,re"))
@@ -5353,7 +5353,7 @@
(set_attr "mode" "DI")])
(define_insn "*adddi_3_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
(match_operand:DI 1 "x86_64_general_operand" "%0")))
(clobber (match_scratch:DI 0 "=r"))]
@@ -5411,7 +5411,7 @@
; Also carry flag is reversed compared to cmp, so this conversion is valid
; only for comparisons not depending on it.
(define_insn "*adddi_4_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:DI 2 "x86_64_immediate_operand" "e")))
(clobber (match_scratch:DI 0 "=rm"))]
@@ -5450,7 +5450,7 @@
(set_attr "mode" "DI")])
(define_insn "*adddi_5_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "x86_64_general_operand" "rme"))
@@ -5650,7 +5650,7 @@
})
(define_insn "*addsi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
(match_operand:SI 2 "general_operand" "rmni,rni"))
@@ -5699,7 +5699,7 @@
;; See comment for addsi_1_zext why we do use nonimmediate_operand
(define_insn "*addsi_2_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "general_operand" "rmni"))
@@ -5743,7 +5743,7 @@
(set_attr "mode" "SI")])
(define_insn "*addsi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
(match_operand:SI 1 "nonimmediate_operand" "%0")))
(clobber (match_scratch:SI 0 "=r"))]
@@ -5789,7 +5789,7 @@
;; See comment for addsi_1_zext why we do use nonimmediate_operand
(define_insn "*addsi_3_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
(match_operand:SI 1 "nonimmediate_operand" "%0")))
(set (match_operand:DI 0 "register_operand" "=r")
@@ -5839,7 +5839,7 @@
; Also carry flag is reversed compared to cmp, so this conversion is valid
; only for comparisons not depending on it.
(define_insn "*addsi_4"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_scratch:SI 0 "=rm"))]
@@ -5876,7 +5876,7 @@
(set_attr "mode" "SI")])
(define_insn "*addsi_5"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "general_operand" "rmni"))
@@ -6013,7 +6013,7 @@
(set_attr "mode" "HI")])
(define_insn "*addhi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
(match_operand:HI 2 "general_operand" "rmni,rni"))
@@ -6053,7 +6053,7 @@
(set_attr "mode" "HI")])
(define_insn "*addhi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
(match_operand:HI 1 "nonimmediate_operand" "%0")))
(clobber (match_scratch:HI 0 "=r"))]
@@ -6091,7 +6091,7 @@
; See comments above addsi_3_imm for details.
(define_insn "*addhi_4"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:HI 2 "const_int_operand" "n")))
(clobber (match_scratch:HI 0 "=rm"))]
@@ -6129,7 +6129,7 @@
(define_insn "*addhi_5"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
(match_operand:HI 2 "general_operand" "rmni"))
@@ -6303,7 +6303,7 @@
(set_attr "mode" "QI")])
(define_insn "*addqi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
(match_operand:QI 2 "general_operand" "qmni,qni"))
@@ -6342,7 +6342,7 @@
(set_attr "mode" "QI")])
(define_insn "*addqi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
(match_operand:QI 1 "nonimmediate_operand" "%0")))
(clobber (match_scratch:QI 0 "=q"))]
@@ -6379,7 +6379,7 @@
; See comments above addsi_3_imm for details.
(define_insn "*addqi_4"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_operand" "n")))
(clobber (match_scratch:QI 0 "=qm"))]
@@ -6417,7 +6417,7 @@
(define_insn "*addqi_5"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
(match_operand:QI 2 "general_operand" "qmni"))
@@ -6625,7 +6625,7 @@
(set_attr "mode" "DI")])
(define_insn "*subdi_2_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:DI 2 "x86_64_general_operand" "re,rm"))
@@ -6639,7 +6639,7 @@
(set_attr "mode" "DI")])
(define_insn "*subdi_3_rex63"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:DI 2 "x86_64_general_operand" "re,rm")))
(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
@@ -6729,7 +6729,7 @@
(set_attr "mode" "SI")])
(define_insn "*subsi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:SI 2 "general_operand" "ri,rm"))
@@ -6743,7 +6743,7 @@
(set_attr "mode" "SI")])
(define_insn "*subsi_2_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(minus:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "rim"))
@@ -6759,7 +6759,7 @@
(set_attr "mode" "SI")])
(define_insn "*subsi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:SI 2 "general_operand" "ri,rm")))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
@@ -6771,7 +6771,7 @@
(set_attr "mode" "SI")])
(define_insn "*subsi_3_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "rim")))
(set (match_operand:DI 0 "register_operand" "=r")
@@ -6803,7 +6803,7 @@
(set_attr "mode" "HI")])
(define_insn "*subhi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
(match_operand:HI 2 "general_operand" "ri,rm"))
@@ -6817,7 +6817,7 @@
(set_attr "mode" "HI")])
(define_insn "*subhi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
(match_operand:HI 2 "general_operand" "ri,rm")))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
@@ -6858,7 +6858,7 @@
(set_attr "mode" "QI")])
(define_insn "*subqi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "general_operand" "qi,qm"))
@@ -6872,7 +6872,7 @@
(set_attr "mode" "QI")])
(define_insn "*subqi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "general_operand" "qi,qm")))
(set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
@@ -7772,7 +7772,7 @@
;; Note that this excludes ah.
(define_insn "*testdi_1_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
(match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
@@ -7791,7 +7791,7 @@
(set_attr "pent_pair" "uv,np,uv,np,uv")])
(define_insn "testsi_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
(match_operand:SI 1 "general_operand" "in,in,rin"))
@@ -7814,7 +7814,7 @@
"")
(define_insn "*testhi_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
(match_operand:HI 1 "general_operand" "n,n,rn"))
(const_int 0)))]
@@ -7870,7 +7870,7 @@
"")
(define_insn "*testqi_ext_0"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(and:SI
(zero_extract:SI
@@ -7887,7 +7887,7 @@
(set_attr "pent_pair" "np")])
(define_insn "*testqi_ext_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(and:SI
(zero_extract:SI
@@ -7904,7 +7904,7 @@
(set_attr "mode" "QI")])
(define_insn "*testqi_ext_1_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(and:SI
(zero_extract:SI
@@ -7920,7 +7920,7 @@
(set_attr "mode" "QI")])
(define_insn "*testqi_ext_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(and:SI
(zero_extract:SI
@@ -7939,7 +7939,7 @@
;; Combine likes to form bit extractions for some tests. Humor it.
(define_insn "*testqi_ext_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (zero_extract:SI
(match_operand 0 "nonimmediate_operand" "rm")
(match_operand:SI 1 "const_int_operand" "")
@@ -7953,7 +7953,7 @@
"#")
(define_insn "*testqi_ext_3_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (zero_extract:DI
(match_operand 0 "nonimmediate_operand" "rm")
(match_operand:DI 1 "const_int_operand" "")
@@ -7974,7 +7974,7 @@
"#")
(define_split
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (zero_extract
(match_operand 0 "nonimmediate_operand" "")
(match_operand 1 "const_int_operand" "")
@@ -8027,7 +8027,7 @@
;; Do the conversion only post-reload to avoid limiting of the register class
;; to QI regs.
(define_split
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(and (match_operand 0 "register_operand" "")
(match_operand 1 "const_int_operand" ""))
@@ -8048,7 +8048,7 @@
operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
(define_split
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(and (match_operand 0 "nonimmediate_operand" "")
(match_operand 1 "const_int_operand" ""))
@@ -8124,7 +8124,7 @@
(set_attr "mode" "SI,DI,DI,DI")])
(define_insn "*anddi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
(const_int 0)))
@@ -8236,7 +8236,7 @@
(set_attr "mode" "SI")])
(define_insn "*andsi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
(match_operand:SI 2 "general_operand" "rim,ri"))
(const_int 0)))
@@ -8250,7 +8250,7 @@
;; See comment for addsi_1_zext why we do use nonimmediate_operand
(define_insn "*andsi_2_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "general_operand" "rim"))
(const_int 0)))
@@ -8298,7 +8298,7 @@
(set_attr "mode" "HI,HI,SI")])
(define_insn "*andhi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
(match_operand:HI 2 "general_operand" "rim,ri"))
(const_int 0)))
@@ -8344,7 +8344,7 @@
(set_attr "mode" "QI")])
(define_insn "*andqi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and:QI
(match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "qim,qi,i"))
@@ -8367,7 +8367,7 @@
(set_attr "mode" "QI,QI,SI")])
(define_insn "*andqi_2_slp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and:QI
(match_operand:QI 0 "nonimmediate_operand" "+q,qm")
(match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
@@ -8406,7 +8406,7 @@
;; often in fp comparisons.
(define_insn "*andqi_ext_0_cc"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(and:SI
(zero_extract:SI
@@ -8556,7 +8556,7 @@
(set_attr "mode" "DI")])
(define_insn "*iordi_2_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "x86_64_general_operand" "rem,re"))
(const_int 0)))
@@ -8570,7 +8570,7 @@
(set_attr "mode" "DI")])
(define_insn "*iordi_3_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "x86_64_general_operand" "rem"))
(const_int 0)))
@@ -8624,7 +8624,7 @@
(set_attr "mode" "SI")])
(define_insn "*iorsi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
(match_operand:SI 2 "general_operand" "rim,ri"))
(const_int 0)))
@@ -8639,7 +8639,7 @@
;; See comment for addsi_1_zext why we do use nonimmediate_operand
;; ??? Special case for immediate operand is missing - it is tricky.
(define_insn "*iorsi_2_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "general_operand" "rim"))
(const_int 0)))
@@ -8652,7 +8652,7 @@
(set_attr "mode" "SI")])
(define_insn "*iorsi_2_zext_imm"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand 2 "x86_64_zext_immediate_operand" "Z"))
(const_int 0)))
@@ -8665,7 +8665,7 @@
(set_attr "mode" "SI")])
(define_insn "*iorsi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "general_operand" "rim"))
(const_int 0)))
@@ -8695,7 +8695,7 @@
(set_attr "mode" "HI")])
(define_insn "*iorhi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
(match_operand:HI 2 "general_operand" "rim,ri"))
(const_int 0)))
@@ -8708,7 +8708,7 @@
(set_attr "mode" "HI")])
(define_insn "*iorhi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
(match_operand:HI 2 "general_operand" "rim"))
(const_int 0)))
@@ -8753,7 +8753,7 @@
(set_attr "mode" "QI")])
(define_insn "*iorqi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
(match_operand:QI 2 "general_operand" "qim,qi"))
(const_int 0)))
@@ -8766,7 +8766,7 @@
(set_attr "mode" "QI")])
(define_insn "*iorqi_2_slp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
(match_operand:QI 1 "general_operand" "qim,qi"))
(const_int 0)))
@@ -8780,7 +8780,7 @@
(set_attr "mode" "QI")])
(define_insn "*iorqi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
(match_operand:QI 2 "general_operand" "qim"))
(const_int 0)))
@@ -8931,7 +8931,7 @@
(set_attr "mode" "DI,DI")])
(define_insn "*xordi_2_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "x86_64_general_operand" "rem,re"))
(const_int 0)))
@@ -8947,7 +8947,7 @@
(set_attr "mode" "DI,DI")])
(define_insn "*xordi_3_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "x86_64_general_operand" "rem"))
(const_int 0)))
@@ -9001,7 +9001,7 @@
(set_attr "mode" "SI")])
(define_insn "*xorsi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
(match_operand:SI 2 "general_operand" "rim,ri"))
(const_int 0)))
@@ -9016,7 +9016,7 @@
;; See comment for addsi_1_zext why we do use nonimmediate_operand
;; ??? Special case for immediate operand is missing - it is tricky.
(define_insn "*xorsi_2_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "general_operand" "rim"))
(const_int 0)))
@@ -9029,7 +9029,7 @@
(set_attr "mode" "SI")])
(define_insn "*xorsi_2_zext_imm"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand 2 "x86_64_zext_immediate_operand" "Z"))
(const_int 0)))
@@ -9042,7 +9042,7 @@
(set_attr "mode" "SI")])
(define_insn "*xorsi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "general_operand" "rim"))
(const_int 0)))
@@ -9072,7 +9072,7 @@
(set_attr "mode" "HI")])
(define_insn "*xorhi_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
(match_operand:HI 2 "general_operand" "rim,ri"))
(const_int 0)))
@@ -9085,7 +9085,7 @@
(set_attr "mode" "HI")])
(define_insn "*xorhi_3"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
(match_operand:HI 2 "general_operand" "rim"))
(const_int 0)))
@@ -9203,7 +9203,7 @@
(set_attr "mode" "QI")])
(define_insn "*xorqi_cc_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
(match_operand:QI 2 "general_operand" "qim,qi"))
@@ -9217,7 +9217,7 @@
(set_attr "mode" "QI")])
(define_insn "*xorqi_2_slp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
(match_operand:QI 1 "general_operand" "qim,qi"))
(const_int 0)))
@@ -9231,7 +9231,7 @@
(set_attr "mode" "QI")])
(define_insn "*xorqi_cc_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
(match_operand:QI 2 "general_operand" "qim"))
@@ -9244,7 +9244,7 @@
(set_attr "mode" "QI")])
(define_insn "*xorqi_cc_ext_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(xor:SI
(zero_extract:SI
@@ -9265,7 +9265,7 @@
(set_attr "mode" "QI")])
(define_insn "*xorqi_cc_ext_1_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(xor:SI
(zero_extract:SI
@@ -10325,7 +10325,7 @@
(set_attr "mode" "DI")])
(define_insn "*one_cmpldi2_2_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
(const_int 0)))
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
@@ -10337,7 +10337,7 @@
(set_attr "mode" "DI")])
(define_split
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
(const_int 0)))
(set (match_operand:DI 0 "nonimmediate_operand" "")
@@ -10374,7 +10374,7 @@
(set_attr "mode" "SI")])
(define_insn "*one_cmplsi2_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
@@ -10386,7 +10386,7 @@
(set_attr "mode" "SI")])
(define_split
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -10401,7 +10401,7 @@
;; ??? Currently never generated - xor is used instead.
(define_insn "*one_cmplsi2_2_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (not:SI (match_operand:SI 1 "register_operand" "0"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
@@ -10413,7 +10413,7 @@
(set_attr "mode" "SI")])
(define_split
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (not:SI (match_operand:SI 1 "register_operand" ""))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "")
@@ -10441,7 +10441,7 @@
(set_attr "mode" "HI")])
(define_insn "*one_cmplhi2_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
@@ -10453,7 +10453,7 @@
(set_attr "mode" "HI")])
(define_split
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -10484,7 +10484,7 @@
(set_attr "mode" "QI,SI")])
(define_insn "*one_cmplqi2_2"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
@@ -10496,7 +10496,7 @@
(set_attr "mode" "QI")])
(define_split
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -10603,7 +10603,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashldi3_cmp_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "immediate_operand" "e"))
@@ -10881,7 +10881,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashlsi3_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -10919,7 +10919,7 @@
(set_attr "mode" "SI")])
(define_insn "*ashlsi3_cmp_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashift:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -11041,7 +11041,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashlhi3_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -11202,7 +11202,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashlqi3_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -11295,7 +11295,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashrdi3_one_bit_cmp_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
@@ -11316,7 +11316,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashrdi3_cmp_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_operand" "n"))
@@ -11499,7 +11499,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashrsi3_one_bit_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
@@ -11517,7 +11517,7 @@
(const_string "*")))])
(define_insn "*ashrsi3_one_bit_cmp_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
@@ -11535,7 +11535,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashrsi3_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -11549,7 +11549,7 @@
(set_attr "mode" "SI")])
(define_insn "*ashrsi3_cmp_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -11600,7 +11600,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashrhi3_one_bit_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
@@ -11621,7 +11621,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashrhi3_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -11700,7 +11700,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashrqi3_one_bit_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "I"))
@@ -11721,7 +11721,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*ashrqi3_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -11775,7 +11775,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*lshrdi3_cmp_one_bit_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
@@ -11796,7 +11796,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*lshrdi3_cmp_rex64"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_operand" "e"))
@@ -11903,7 +11903,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*lshrsi3_one_bit_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
@@ -11921,7 +11921,7 @@
(const_string "*")))])
(define_insn "*lshrsi3_cmp_one_bit_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
@@ -11939,7 +11939,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*lshrsi3_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -11953,7 +11953,7 @@
(set_attr "mode" "SI")])
(define_insn "*lshrsi3_cmp_zext"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -12004,7 +12004,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*lshrhi3_one_bit_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
@@ -12025,7 +12025,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*lshrhi3_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -12103,7 +12103,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*lshrqi2_one_bit_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" ""))
@@ -12124,7 +12124,7 @@
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
(define_insn "*lshrqi2_cmp"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_31_operand" "I"))
@@ -12700,7 +12700,7 @@
(define_insn "*setcc_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(match_operator:QI 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)]))]
+ [(reg FLAGS_REG) (const_int 0)]))]
""
"set%C1\t%0"
[(set_attr "type" "setcc")
@@ -12709,7 +12709,7 @@
(define_insn "*setcc_2"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(match_operator:QI 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)]))]
+ [(reg FLAGS_REG) (const_int 0)]))]
""
"set%C1\t%0"
[(set_attr "type" "setcc")
@@ -12726,7 +12726,7 @@
(define_split
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(ne:QI (match_operator 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
""
[(set (match_dup 0) (match_dup 1))]
@@ -12737,7 +12737,7 @@
(define_split
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
(ne:QI (match_operator 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
""
[(set (match_dup 0) (match_dup 1))]
@@ -12748,7 +12748,7 @@
(define_split
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(eq:QI (match_operator 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
""
[(set (match_dup 0) (match_dup 1))]
@@ -12768,7 +12768,7 @@
(define_split
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
(eq:QI (match_operator 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
""
[(set (match_dup 0) (match_dup 1))]
@@ -12817,7 +12817,7 @@
;; We ignore the overflow flag for signed branch instructions.
;; For all bCOND expanders, also expand the compare or test insn that
-;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
+;; generates reg FLAGS_REG. Generate an equality comparison if `beq' or `bne'.
(define_expand "beq"
[(set (pc)
@@ -12966,7 +12966,7 @@
(define_insn "*jcc_1"
[(set (pc)
(if_then_else (match_operator 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
""
@@ -12984,7 +12984,7 @@
(define_insn "*jcc_2"
[(set (pc)
(if_then_else (match_operator 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
""
@@ -13010,7 +13010,7 @@
(define_split
[(set (pc)
(if_then_else (ne (match_operator 0 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
@@ -13026,7 +13026,7 @@
(define_split
[(set (pc)
(if_then_else (eq (match_operator 0 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
@@ -13532,10 +13532,10 @@
;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
(define_peephole2
- [(set (reg 17) (match_operand 0 "" ""))
+ [(set (reg FLAGS_REG) (match_operand 0 "" ""))
(set (match_operand:QI 1 "register_operand" "")
(match_operator:QI 2 "ix86_comparison_operator"
- [(reg 17) (const_int 0)]))
+ [(reg FLAGS_REG) (const_int 0)]))
(set (match_operand 3 "q_regs_operand" "")
(zero_extend (match_dup 1)))]
"(peep2_reg_dead_p (3, operands[1])
@@ -13553,10 +13553,10 @@
;; Similar, but match zero_extendhisi2_and, which adds a clobber.
(define_peephole2
- [(set (reg 17) (match_operand 0 "" ""))
+ [(set (reg FLAGS_REG) (match_operand 0 "" ""))
(set (match_operand:QI 1 "register_operand" "")
(match_operator:QI 2 "ix86_comparison_operator"
- [(reg 17) (const_int 0)]))
+ [(reg FLAGS_REG) (const_int 0)]))
(parallel [(set (match_operand 3 "q_regs_operand" "")
(zero_extend (match_dup 1)))
(clobber (reg:CC FLAGS_REG))])]
@@ -14024,7 +14024,7 @@
[(set (match_operand:DI 0 "register_operand" "")
(ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
(clobber (match_scratch:DI 2 ""))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT && TARGET_CMOVE"
"")
@@ -14032,23 +14032,24 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:DI 2 "=&r"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_CMOVE"
"#"
"&& reload_completed"
[(set (match_dup 2) (const_int -1))
- (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
+ (parallel [(set (reg:CCZ FLAGS_REG)
+ (compare:CCZ (match_dup 1) (const_int 0)))
(set (match_dup 0) (ctz:DI (match_dup 1)))])
(set (match_dup 0) (if_then_else:DI
- (eq (reg:CCZ 17) (const_int 0))
+ (eq (reg:CCZ FLAGS_REG) (const_int 0))
(match_dup 2)
(match_dup 0)))
(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_insn "*ffsdi_1"
- [(set (reg:CCZ 17)
+ [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
@@ -14068,7 +14069,7 @@
(define_insn "ctzdi2"
[(set (match_operand:DI 0 "register_operand" "=r")
(ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"bsf{q}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")])
@@ -14099,10 +14100,10 @@
[(set (match_operand:DI 0 "register_operand" "")
(minus:DI (const_int 63)
(clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(parallel
[(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT"
"")
@@ -14110,7 +14111,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (const_int 63)
(clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"bsr{q}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")])
@@ -17555,7 +17556,7 @@
(gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (match_operand:QI 8 "register_operand" "")
(ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
- (set (reg 17)
+ (set (reg FLAGS_REG)
(compare (match_dup 7) (match_dup 8)))
]
"peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
@@ -17590,7 +17591,7 @@
(gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (match_operand:QI 8 "register_operand" "")
(ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
- (set (reg 17)
+ (set (reg FLAGS_REG)
(compare (match_dup 7) (match_dup 8)))
]
"peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
@@ -17641,7 +17642,7 @@
(define_insn "movdicc_c_rex64"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(if_then_else:DI (match_operator 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:DI 2 "nonimmediate_operand" "rm,0")
(match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
"TARGET_64BIT && TARGET_CMOVE
@@ -17684,7 +17685,7 @@
(define_insn "*movsicc_noc"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(if_then_else:SI (match_operator 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:SI 2 "nonimmediate_operand" "rm,0")
(match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
"TARGET_CMOVE
@@ -17706,7 +17707,7 @@
(define_insn "*movhicc_noc"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(if_then_else:HI (match_operator 1 "ix86_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:HI 2 "nonimmediate_operand" "rm,0")
(match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
"TARGET_CMOVE
@@ -17755,7 +17756,7 @@
(define_insn "*movsfcc_1"
[(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
(match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
"TARGET_CMOVE
@@ -17779,7 +17780,7 @@
(define_insn "*movdfcc_1"
[(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
(match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
"!TARGET_64BIT && TARGET_CMOVE
@@ -17795,7 +17796,7 @@
(define_insn "*movdfcc_1_rex64"
[(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
(match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
"TARGET_64BIT && TARGET_CMOVE
@@ -17838,7 +17839,7 @@
(define_insn "*movxfcc_1"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:XF 2 "register_operand" "f,0")
(match_operand:XF 3 "register_operand" "0,f")))]
"TARGET_CMOVE"
@@ -18809,7 +18810,7 @@
; instruction size is unchanged, except in the %eax case for
; which it is increased by one byte, hence the ! optimize_size.
(define_split
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and (match_operand 1 "aligned_operand" "")
(match_operand 2 "const_int_operand" ""))
(const_int 0)))
@@ -18838,7 +18839,7 @@
; the instruction size would at least double, which is not what we
; want even with ! optimize_size.
(define_split
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and (match_operand:HI 0 "aligned_operand" "")
(match_operand:HI 1 "const_int_operand" ""))
(const_int 0)))]
@@ -18885,7 +18886,7 @@
(define_split
[(set (match_operand 0 "register_operand" "")
(if_then_else (match_operator 1 "comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand 2 "register_operand" "")
(match_operand 3 "register_operand" "")))]
"! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
@@ -19027,7 +19028,7 @@
;; Don't compare memory with zero, load and use a test instead.
(define_peephole2
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:SI 0 "memory_operand" "")
(const_int 0)))
(match_scratch:SI 3 "r")]
@@ -19097,7 +19098,7 @@
;; versions if we're concerned about partial register stalls.
(define_peephole2
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and:SI (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "immediate_operand" ""))
(const_int 0)))]
@@ -19119,7 +19120,7 @@
;; on ! TARGET_PARTIAL_REG_STALL
(define_peephole2
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and:QI (match_operand:QI 0 "register_operand" "")
(match_operand:QI 1 "immediate_operand" ""))
(const_int 0)))]
@@ -19137,7 +19138,7 @@
"")
(define_peephole2
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare
(and:SI
(zero_extract:SI
@@ -19471,7 +19472,7 @@
;; Convert compares with 1 to shorter inc/dec operations when CF is not
;; required and register dies.
(define_peephole2
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "incdec_operand" "")))]
"ix86_match_ccmode (insn, CCGCmode)
@@ -19483,7 +19484,7 @@
"")
(define_peephole2
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:HI 0 "register_operand" "")
(match_operand:HI 1 "incdec_operand" "")))]
"ix86_match_ccmode (insn, CCGCmode)
@@ -19495,7 +19496,7 @@
"")
(define_peephole2
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:QI 0 "register_operand" "")
(match_operand:QI 1 "incdec_operand" "")))]
"ix86_match_ccmode (insn, CCGCmode)
@@ -19508,7 +19509,7 @@
;; Convert compares with 128 to shorter add -128
(define_peephole2
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:SI 0 "register_operand" "")
(const_int 128)))]
"ix86_match_ccmode (insn, CCGCmode)
@@ -19520,7 +19521,7 @@
"")
(define_peephole2
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (match_operand:HI 0 "register_operand" "")
(const_int 128)))]
"ix86_match_ccmode (insn, CCGCmode)
@@ -19960,7 +19961,7 @@
(define_insn "*conditional_trap_1"
[(trap_if (match_operator 0 "comparison_operator"
- [(reg 17) (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand 1 "const_int_operand" ""))]
""
{