From 4389a2d2d0cc639cbeeb8453dc20bf315316d4e3 Mon Sep 17 00:00:00 2001
From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Tue, 13 Jun 2023 10:13:55 +0100
Subject: [PATCH] aarch64: Extend -mtp= arguments
After discussing the -mtp= option with Arm's LLVM developers we'd like to extend
the functionality of the option somewhat.
First of all, there is another TPIDR register that can be used to read the thread pointer:
TPIDRRO_EL0 (which can also be accessed by AArch32 under another name) so it makes sense
to add -mtp=tpidrr0_el0. This makes the existing arguments el0, el1, el2, el3 somewhat
inconsistent in their naming so this patch introduces the more "full" names
tpidr_el0, tpidr_el1, tpidr_el2, tpidr_el3 and makes the above short names alias of these new ones.
Long story short, we preserve backwards compatibility and add a new TPIDR register to access through
-mtp that wasn't available previously.
There is more relevant discussion of the options at https://reviews.llvm.org/D152433 if you're interested.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/ChangeLog:
PR target/108779
* config/aarch64/aarch64-opts.h (enum aarch64_tp_reg): Add
AARCH64_TPIDRRO_EL0 value.
* config/aarch64/aarch64.cc (aarch64_output_load_tp): Define.
* config/aarch64/aarch64.opt (tpidr_el0, tpidr_el1, tpidr_el2,
tpidr_el3, tpidrro_el3): New accepted values to -mtp=.
* doc/invoke.texi (AArch64 Options): Document new -mtp= options.
gcc/testsuite/ChangeLog:
PR target/108779
* gcc.target/aarch64/mtp_5.c: New test.
* gcc.target/aarch64/mtp_6.c: New test.
* gcc.target/aarch64/mtp_7.c: New test.
* gcc.target/aarch64/mtp_8.c: New test.
* gcc.target/aarch64/mtp_9.c: New test.
---
gcc/config/aarch64/aarch64-opts.h | 3 ++-
gcc/config/aarch64/aarch64.cc | 3 ++-
gcc/config/aarch64/aarch64.opt | 15 +++++++++++++++
gcc/doc/invoke.texi | 12 ++++++------
gcc/testsuite/gcc.target/aarch64/mtp_5.c | 7 +++++++
gcc/testsuite/gcc.target/aarch64/mtp_6.c | 7 +++++++
gcc/testsuite/gcc.target/aarch64/mtp_7.c | 7 +++++++
gcc/testsuite/gcc.target/aarch64/mtp_8.c | 7 +++++++
gcc/testsuite/gcc.target/aarch64/mtp_9.c | 7 +++++++
9 files changed, 60 insertions(+), 8 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/mtp_5.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/mtp_6.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/mtp_7.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/mtp_8.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/mtp_9.c
diff --git a/gcc/config/aarch64/aarch64-opts.h b/gcc/config/aarch64/aarch64-opts.h
index 9d5bf77c868d..7e8f1babed8e 100644
--- a/gcc/config/aarch64/aarch64-opts.h
+++ b/gcc/config/aarch64/aarch64-opts.h
@@ -81,7 +81,8 @@ enum aarch64_tp_reg {
AARCH64_TPIDR_EL0 = 0,
AARCH64_TPIDR_EL1 = 1,
AARCH64_TPIDR_EL2 = 2,
- AARCH64_TPIDR_EL3 = 3
+ AARCH64_TPIDR_EL3 = 3,
+ AARCH64_TPIDRRO_EL0 = 4
};
/* SVE vector register sizes. */
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 20517c75d808..df37bde6a78c 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -27693,7 +27693,8 @@ aarch64_indirect_call_asm (rtx addr)
const char *
aarch64_output_load_tp (rtx dest)
{
- const char *tpidrs[] = {"tpidr_el0", "tpidr_el1", "tpidr_el2", "tpidr_el3"};
+ const char *tpidrs[] = {"tpidr_el0", "tpidr_el1", "tpidr_el2",
+ "tpidr_el3", "tpidrro_el0"};
char buffer[64];
snprintf (buffer, sizeof (buffer), "mrs\t%%0, %s",
tpidrs[aarch64_tpidr_register]);
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
index 025e52d40e5c..4a0580435a8d 100644
--- a/gcc/config/aarch64/aarch64.opt
+++ b/gcc/config/aarch64/aarch64.opt
@@ -104,15 +104,30 @@ The register used to access the thread pointer:
EnumValue
Enum(tp_reg) String(el0) Value(AARCH64_TPIDR_EL0)
+EnumValue
+Enum(tp_reg) String(tpidr_el0) Value(AARCH64_TPIDR_EL0)
+
EnumValue
Enum(tp_reg) String(el1) Value(AARCH64_TPIDR_EL1)
+EnumValue
+Enum(tp_reg) String(tpidr_el1) Value(AARCH64_TPIDR_EL1)
+
EnumValue
Enum(tp_reg) String(el2) Value(AARCH64_TPIDR_EL2)
+EnumValue
+Enum(tp_reg) String(tpidr_el2) Value(AARCH64_TPIDR_EL2)
+
EnumValue
Enum(tp_reg) String(el3) Value(AARCH64_TPIDR_EL3)
+EnumValue
+Enum(tp_reg) String(tpidr_el3) Value(AARCH64_TPIDR_EL3)
+
+EnumValue
+Enum(tp_reg) String(tpidrro_el0) Value(AARCH64_TPIDRRO_EL0)
+
mtp=
Target RejectNegative Joined Enum(tp_reg) Var(aarch64_tpidr_reg) Init(AARCH64_TPIDR_EL0) Save
Specify the thread pointer register.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0870f7aff936..54c377fd8154 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -20235,12 +20235,12 @@ addresses and sizes of sections. Programs can be statically linked only. The
@item -mtp=@var{name}
@opindex mtp
Specify the system register to use as a thread pointer. The valid values
-are @samp{el0}, @samp{el1}, @samp{el2}, @samp{el3}. These correspond to
-using the @samp{tpidr_el0}, @samp{tpidr_el1}, @samp{tpidr_el2},
-@samp{tpidr_el3} registers accordingly. The default setting is @samp{el0}.
-It is recommended to compile all code intended to interoperate with the same
-value of this option to avoid accessing a different thread pointer from the
-wrong exception level.
+are @samp{tpidr_el0}, @samp{tpidrro_el0}, @samp{tpidr_el1}, @samp{tpidr_el2},
+@samp{tpidr_el3}. For backwards compatibility the aliases @samp{el0},
+@samp{el1}, @samp{el2}, @samp{el3} are also accepted.
+The default setting is @samp{tpidr_el0}. It is recommended to compile all
+code intended to interoperate with the same value of this option to avoid
+accessing a different thread pointer from the wrong exception level.
@opindex mstrict-align
@opindex mno-strict-align
diff --git a/gcc/testsuite/gcc.target/aarch64/mtp_5.c b/gcc/testsuite/gcc.target/aarch64/mtp_5.c
new file mode 100644
index 000000000000..72bd86169a5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mtp_5.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target tls_native } */
+/* { dg-options "-O -mtp=tpidrro_el0" } */
+
+#include "mtp.c"
+
+/* { dg-final { scan-assembler-times {mrs\tx[0-9]+, tpidrro_el0} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/mtp_6.c b/gcc/testsuite/gcc.target/aarch64/mtp_6.c
new file mode 100644
index 000000000000..0cdee12f67dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mtp_6.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target tls_native } */
+/* { dg-options "-O -mtp=tpidr_el0" } */
+
+#include "mtp.c"
+
+/* { dg-final { scan-assembler-times {mrs\tx[0-9]+, tpidr_el0} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/mtp_7.c b/gcc/testsuite/gcc.target/aarch64/mtp_7.c
new file mode 100644
index 000000000000..2e4a1a4ee9b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mtp_7.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target tls_native } */
+/* { dg-options "-O -mtp=tpidr_el1" } */
+
+#include "mtp.c"
+
+/* { dg-final { scan-assembler-times {mrs\tx[0-9]+, tpidr_el1} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/mtp_8.c b/gcc/testsuite/gcc.target/aarch64/mtp_8.c
new file mode 100644
index 000000000000..810fe38de9d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mtp_8.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target tls_native } */
+/* { dg-options "-O -mtp=tpidr_el2" } */
+
+#include "mtp.c"
+
+/* { dg-final { scan-assembler-times {mrs\tx[0-9]+, tpidr_el2} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/mtp_9.c b/gcc/testsuite/gcc.target/aarch64/mtp_9.c
new file mode 100644
index 000000000000..934cc18cbe8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mtp_9.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target tls_native } */
+/* { dg-options "-O -mtp=tpidr_el3" } */
+
+#include "mtp.c"
+
+/* { dg-final { scan-assembler-times {mrs\tx[0-9]+, tpidr_el3} 1 } } */
--
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