diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5a7c5bdaa25461f05ef42f1ac4614b22b51be56b..ec8b683b9460f5fdcfcbf1acb8f4c5be1061d7ac 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2012-07-01 Wei Guozhi <carrot@google.com>
+
+ PR target/53447
+ * config/arm/arm-protos.h (const_ok_for_dimode_op): New prototype.
+ * config/arm/arm.c (const_ok_for_dimode_op): New function.
+ * config/arm/constraints.md (Dd): New constraint.
+ * config/arm/predicates.md (arm_adddi_operand): New predicate.
+ * config/arm/arm.md (adddi3): Extend it to handle constants.
+ (arm_adddi3): Likewise.
+ (addsi3_carryin_<optab>): Extend it to handle sbc case.
+ (addsi3_carryin_alt2_<optab>): Likewise.
+ * config/arm/neon.md (adddi3_neon): Extend it to handle constants.
+
2012-06-30 Nathan Sidwell <nathan@acm.org>
* coverage.c (bbg_file_stamp): New.
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index ba5802e8cb2e9aef21816c1d312e46a717382c94..3cc4adb8e3765bc36aaccb83d7213b495f177d9d 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -50,6 +50,7 @@ extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode);
extern bool arm_modes_tieable_p (enum machine_mode, enum machine_mode);
extern int const_ok_for_arm (HOST_WIDE_INT);
extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
+extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
HOST_WIDE_INT, rtx, rtx, int);
extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a385e304a36d1539c307bfc1344b3145fb19a93c..6472b6147cd813370aab8392d6e590f75544246c 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2507,6 +2507,28 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
}
}
+/* Return true if I is a valid di mode constant for the operation CODE. */
+int
+const_ok_for_dimode_op (HOST_WIDE_INT i, enum rtx_code code)
+{
+ HOST_WIDE_INT hi_val = (i >> 32) & 0xFFFFFFFF;
+ HOST_WIDE_INT lo_val = i & 0xFFFFFFFF;
+ rtx hi = GEN_INT (hi_val);
+ rtx lo = GEN_INT (lo_val);
+
+ if (TARGET_THUMB1)
+ return 0;
+
+ switch (code)
+ {
+ case PLUS:
+ return arm_not_operand (hi, SImode) && arm_add_operand (lo, SImode);
+
+ default:
+ return 0;
+ }
+}
+
/* Emit a sequence of insns to handle a large constant.
CODE is the code of the operation required, it can be any of SET, PLUS,
IOR, AND, XOR, MINUS;
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 0654564de1b3efc5b70dfcf288eb2efd9b7fa131..15d2ce502cb3477b4b62d28e285f6fb81d2c8f34 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -604,7 +604,7 @@
[(parallel
[(set (match_operand:DI 0 "s_register_operand" "")
(plus:DI (match_operand:DI 1 "s_register_operand" "")
- (match_operand:DI 2 "s_register_operand" "")))
+ (match_operand:DI 2 "arm_adddi_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_EITHER"
"
@@ -630,9 +630,9 @@
)
(define_insn_and_split "*arm_adddi3"
- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
- (match_operand:DI 2 "s_register_operand" "r, 0")))
+ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r,&r,&r")
+ (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0, r, 0, r")
+ (match_operand:DI 2 "arm_adddi_operand" "r, 0, r, Dd, Dd")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && !TARGET_NEON"
"#"
@@ -650,7 +650,7 @@
operands[0] = gen_lowpart (SImode, operands[0]);
operands[4] = gen_highpart (SImode, operands[1]);
operands[1] = gen_lowpart (SImode, operands[1]);
- operands[5] = gen_highpart (SImode, operands[2]);
+ operands[5] = gen_highpart_mode (SImode, DImode, operands[2]);
operands[2] = gen_lowpart (SImode, operands[2]);
}"
[(set_attr "conds" "clob")
@@ -1001,22 +1001,26 @@
)
(define_insn "*addsi3_carryin_<optab>"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
- (match_operand:SI 2 "arm_rhs_operand" "rI"))
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r,r")
+ (match_operand:SI 2 "arm_not_operand" "rI,K"))
(LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
"TARGET_32BIT"
- "adc%?\\t%0, %1, %2"
+ "@
+ adc%?\\t%0, %1, %2
+ sbc%?\\t%0, %1, #%B2"
[(set_attr "conds" "use")]
)
(define_insn "*addsi3_carryin_alt2_<optab>"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
- (match_operand:SI 1 "s_register_operand" "%r"))
- (match_operand:SI 2 "arm_rhs_operand" "rI")))]
+ (match_operand:SI 1 "s_register_operand" "%r,r"))
+ (match_operand:SI 2 "arm_rhs_operand" "rI,K")))]
"TARGET_32BIT"
- "adc%?\\t%0, %1, %2"
+ "@
+ adc%?\\t%0, %1, %2
+ sbc%?\\t%0, %1, #%B2"
[(set_attr "conds" "use")]
)
diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index c1d881e5e8637f881deb1bc78c817c7f7005d802..b67df55dd1697e7d530b384bf4108c16826f6719 100644
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -31,7 +31,7 @@
;; 'H' was previously used for FPA.
;; The following multi-letter normal constraints have been used:
-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
+;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
@@ -242,6 +242,12 @@
(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
&& !(optimize_size || arm_ld_sched)")))
+(define_constraint "Dd"
+ "@internal
+ In ARM/Thumb-2 state a const_int that can be used by insn adddi."
+ (and (match_code "const_int")
+ (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
+
(define_constraint "Di"
"@internal
In ARM/Thumb-2 state a const_int or const_double where both the high
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index b3b925cff42c694bb37af94968ddaaec85b4e5d8..168b5be1e445bd55de0755c46211062a56d9a299 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -587,9 +587,9 @@
)
(define_insn "adddi3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w")
- (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,w")
- (match_operand:DI 2 "s_register_operand" "w,r,0,w")))
+ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w,?&r,?&r,?&r")
+ (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,w,r,0,r")
+ (match_operand:DI 2 "arm_adddi_operand" "w,r,0,w,r,Dd,Dd")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_NEON"
{
@@ -599,13 +599,16 @@
case 3: return "vadd.i64\t%P0, %P1, %P2";
case 1: return "#";
case 2: return "#";
+ case 4: return "#";
+ case 5: return "#";
+ case 6: return "#";
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1")
- (set_attr "conds" "*,clob,clob,*")
- (set_attr "length" "*,8,8,*")
- (set_attr "arch" "nota8,*,*,onlya8")]
+ [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1,*,*,*")
+ (set_attr "conds" "*,clob,clob,*,clob,clob,clob")
+ (set_attr "length" "*,8,8,*,8,8,8")
+ (set_attr "arch" "nota8,*,*,onlya8,*,*,*")]
)
(define_insn "*sub<mode>3_neon"
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 9fd9ad216fc06e56fb5d44b4b6a01033023d59f4..8ae26cae7a7de218fdba1140f66d859e01f4a4aa 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -141,6 +141,11 @@
(ior (match_operand 0 "arm_rhs_operand")
(match_operand 0 "arm_neg_immediate_operand")))
+(define_predicate "arm_adddi_operand"
+ (ior (match_operand 0 "s_register_operand")
+ (and (match_code "const_int")
+ (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
+
(define_predicate "arm_addimm_operand"
(ior (match_operand 0 "arm_immediate_operand")
(match_operand 0 "arm_neg_immediate_operand")))
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 673b53251698411c6f73554c58f4f621ae1d8a0a..159b0f63186b010834720528e1536df7fc4d9e5e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2012-07-01 Wei Guozhi <carrot@google.com>
+
+ PR target/53447
+ * gcc.target/arm/pr53447-1.c: New testcase.
+ * gcc.target/arm/pr53447-2.c: New testcase.
+ * gcc.target/arm/pr53447-3.c: New testcase.
+ * gcc.target/arm/pr53447-4.c: New testcase.
+
2012-06-29 Richard Guenther <rguenther@suse.de>
PR tree-optimization/47061
diff --git a/gcc/testsuite/gcc.target/arm/pr53447-1.c b/gcc/testsuite/gcc.target/arm/pr53447-1.c
new file mode 100644
index 0000000000000000000000000000000000000000..dc094180c85092febd18be7eef2887e6f1d7640f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr53447-1.c
@@ -0,0 +1,8 @@
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+void t0p(long long * p)
+{
+ *p += 0x100000001;
+}
diff --git a/gcc/testsuite/gcc.target/arm/pr53447-2.c b/gcc/testsuite/gcc.target/arm/pr53447-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..9a2b0315c1a7bcd53ded02949451f88e6e9bc182
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr53447-2.c
@@ -0,0 +1,8 @@
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+void t0p(long long * p)
+{
+ *p -= 0x100000008;
+}
diff --git a/gcc/testsuite/gcc.target/arm/pr53447-3.c b/gcc/testsuite/gcc.target/arm/pr53447-3.c
new file mode 100644
index 0000000000000000000000000000000000000000..8e48f119b748244a4032a9ab39fcae022d7527e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr53447-3.c
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+
+void t0p(long long * p)
+{
+ *p +=0x1fffffff8;
+}
diff --git a/gcc/testsuite/gcc.target/arm/pr53447-4.c b/gcc/testsuite/gcc.target/arm/pr53447-4.c
new file mode 100644
index 0000000000000000000000000000000000000000..22acb97270e2eec424be5cd6a82ee65bca07f72e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr53447-4.c
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+
+void t0p(long long * p)
+{
+ *p -=0x1fffffff8;
+}