From 4b3c2e48c46352fc7b22bbce659422d07dac5604 Mon Sep 17 00:00:00 2001
From: Philip Blundell <philb@gnu.org>
Date: Thu, 15 May 2003 18:38:21 +0000
Subject: [PATCH] arm.c (arm_is_xscale): Rename to arm_arch_xscale.
2003-05-15 Philip Blundell <philb@gnu.org>
* config/arm/arm.c (arm_is_xscale): Rename to arm_arch_xscale.
All uses updated.
(arm_tune_xscale): New variable.
(arm_override_options): Set it.
(arm_adjust_cost): Use it in place of arm_arch_xscale.
(arm_gen_load_multiple): Likewise.
(arm_gen_store_multiple): Likewise.
* config/arm/arm.md (is_xscale): Likewise.
* config/arm/arm.h (arm_tune_xscale): Declare.
From-SVN: r66839
---
gcc/ChangeLog | 12 ++++++++++++
gcc/config/arm/arm.c | 16 ++++++++++------
gcc/config/arm/arm.h | 9 ++++++---
gcc/config/arm/arm.md | 10 +++++-----
4 files changed, 33 insertions(+), 14 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 772b5e0a50a8..34752f14fec1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2003-05-15 Philip Blundell <philb@gnu.org>
+
+ * config/arm/arm.c (arm_is_xscale): Rename to arm_arch_xscale.
+ All uses updated.
+ (arm_tune_xscale): New variable.
+ (arm_override_options): Set it.
+ (arm_adjust_cost): Use it in place of arm_arch_xscale.
+ (arm_gen_load_multiple): Likewise.
+ (arm_gen_store_multiple): Likewise.
+ * config/arm/arm.md (is_xscale): Likewise.
+ * config/arm/arm.h (arm_tune_xscale): Declare.
+
2003-05-15 Philip Blundell <philb@gnu.org>
PR target/10730
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index d776766dc7f1..2dcb226e661a 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -303,7 +303,10 @@ int arm_ld_sched = 0;
int arm_is_strong = 0;
/* Nonzero if this chip is an XScale. */
-int arm_is_xscale = 0;
+int arm_arch_xscale = 0;
+
+/* Nonzero if tuning for XScale */
+int arm_tune_xscale = 0;
/* Nonzero if this chip is an ARM6 or an ARM7. */
int arm_is_6_or_7 = 0;
@@ -718,13 +721,14 @@ arm_override_options ()
arm_arch4 = (insn_flags & FL_ARCH4) != 0;
arm_arch5 = (insn_flags & FL_ARCH5) != 0;
arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
- arm_is_xscale = (insn_flags & FL_XSCALE) != 0;
+ arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
arm_is_strong = (tune_flags & FL_STRONG) != 0;
thumb_code = (TARGET_ARM == 0);
arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
&& !(tune_flags & FL_ARCH4))) != 0;
+ arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
arm_is_cirrus = (tune_flags & FL_CIRRUS) != 0;
if (arm_is_cirrus)
@@ -813,7 +817,7 @@ arm_override_options ()
if (optimize_size || (tune_flags & FL_LDSCHED))
arm_constant_limit = 1;
- if (arm_is_xscale)
+ if (arm_arch_xscale)
arm_constant_limit = 2;
/* If optimizing for size, bump the number of instructions that we
@@ -3475,7 +3479,7 @@ arm_adjust_cost (insn, link, dep, cost)
/* Some true dependencies can have a higher cost depending
on precisely how certain input operands are used. */
- if (arm_is_xscale
+ if (arm_tune_xscale
&& REG_NOTE_KIND (link) == 0
&& recog_memoized (insn) >= 0
&& recog_memoized (dep) >= 0)
@@ -5187,7 +5191,7 @@ arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
for counts of 3 or 4 regs. */
- if (arm_is_xscale && count <= 2 && ! optimize_size)
+ if (arm_tune_xscale && count <= 2 && ! optimize_size)
{
rtx seq;
@@ -5254,7 +5258,7 @@ arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
/* See arm_gen_load_multiple for discussion of
the pros/cons of ldm/stm usage for XScale. */
- if (arm_is_xscale && count <= 2 && ! optimize_size)
+ if (arm_tune_xscale && count <= 2 && ! optimize_size)
{
rtx seq;
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index eb2bfa0b71af..cf6b91f6ce18 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -610,7 +610,10 @@ extern int arm_is_strong;
extern int arm_is_cirrus;
/* Nonzero if this chip is an XScale. */
-extern int arm_is_xscale;
+extern int arm_arch_xscale;
+
+/* Nonzero if tuning for XScale */
+extern int arm_tune_xscale;
/* Nonzero if this chip is an ARM6 or an ARM7. */
extern int arm_is_6_or_7;
@@ -728,7 +731,7 @@ extern int arm_is_6_or_7;
#define BIGGEST_ALIGNMENT 32
/* Make strings word-aligned so strcpy from constants will be faster. */
-#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
+#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_arch_xscale ? 1 : 2)
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
((TREE_CODE (EXP) == STRING_CST \
@@ -2119,7 +2122,7 @@ do { \
#define MOVE_MAX 4
#undef MOVE_RATIO
-#define MOVE_RATIO (arm_is_xscale ? 4 : 2)
+#define MOVE_RATIO (arm_arch_xscale ? 4 : 2)
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 6fb75d0d93db..49f41c69169f 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -121,7 +121,7 @@
;; Operand number of an input operand that is shifted. Zero if the
;; given instruction does not shift one of its input operands.
-(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_is_xscale")))
+(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale")))
(define_attr "shift" "" (const_int 0))
; Floating Point Unit. If we only have floating point emulation, then there
@@ -1082,7 +1082,7 @@
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
(mult:SI (match_dup 2) (match_dup 1)))]
- "TARGET_ARM && !arm_is_xscale"
+ "TARGET_ARM && !arm_arch_xscale"
"mul%?s\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "type" "mult")]
@@ -1095,7 +1095,7 @@
(match_operand:SI 1 "s_register_operand" "%?r,0"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=&r,&r"))]
- "TARGET_ARM && !arm_is_xscale"
+ "TARGET_ARM && !arm_arch_xscale"
"mul%?s\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "type" "mult")]
@@ -1126,7 +1126,7 @@
(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
(plus:SI (mult:SI (match_dup 2) (match_dup 1))
(match_dup 3)))]
- "TARGET_ARM && !arm_is_xscale"
+ "TARGET_ARM && !arm_arch_xscale"
"mla%?s\\t%0, %2, %1, %3"
[(set_attr "conds" "set")
(set_attr "type" "mult")]
@@ -1141,7 +1141,7 @@
(match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
- "TARGET_ARM && !arm_is_xscale"
+ "TARGET_ARM && !arm_arch_xscale"
"mla%?s\\t%0, %2, %1, %3"
[(set_attr "conds" "set")
(set_attr "type" "mult")]
--
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