From 4e1b617b35631df4dd6089d4044aa19d0c1adea7 Mon Sep 17 00:00:00 2001
From: Andrew Carlotti <andrew.carlotti@arm.com>
Date: Tue, 18 Jul 2023 20:09:38 +0100
Subject: [PATCH] aarch64: Fix memtag intrinsic availability
The availability of memtag intrinsics and data types were determined
solely by the globally specified architecture features, which did not
reflect any changes specified in target pragmas or attributes.
This patch removes the initialisation-time guards for the intrinsics,
and replaces them with checks at use time. It also removes the macro
indirection from the header file - this simplifies the header, and
allows the missing extension error reporting to find the user-facing
intrinsic names.
gcc/ChangeLog:
PR target/112108
* config/aarch64/aarch64-builtins.cc (aarch64_init_memtag_builtins):
Define intrinsic names directly.
(aarch64_general_init_builtins): Move memtag intialisation...
(handle_arm_acle_h): ...to here, and remove feature check.
(aarch64_general_check_builtin_call): Check memtag intrinsics.
* config/aarch64/arm_acle.h (__arm_mte_create_random_tag)
(__arm_mte_exclude_tag, __arm_mte_ptrdiff)
(__arm_mte_increment_tag, __arm_mte_set_tag, __arm_mte_get_tag):
Remove.
gcc/testsuite/ChangeLog:
PR target/112108
* gcc.target/aarch64/acle/memtag_guard-1.c: New test.
* gcc.target/aarch64/acle/memtag_guard-2.c: New test.
* gcc.target/aarch64/acle/memtag_guard-3.c: New test.
* gcc.target/aarch64/acle/memtag_guard-4.c: New test.
---
gcc/config/aarch64/aarch64-builtins.cc | 23 +++++++++++--------
gcc/config/aarch64/arm_acle.h | 23 -------------------
.../gcc.target/aarch64/acle/memtag_guard-1.c | 9 ++++++++
.../gcc.target/aarch64/acle/memtag_guard-2.c | 10 ++++++++
.../gcc.target/aarch64/acle/memtag_guard-3.c | 9 ++++++++
.../gcc.target/aarch64/acle/memtag_guard-4.c | 10 ++++++++
6 files changed, 51 insertions(+), 33 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-4.c
diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
index 60e4c217921b..9c6d9ec7537e 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -1932,27 +1932,27 @@ aarch64_init_memtag_builtins (void)
#define AARCH64_INIT_MEMTAG_BUILTINS_DECL(F, N, I, T) \
aarch64_builtin_decls[AARCH64_MEMTAG_BUILTIN_##F] \
- = aarch64_general_add_builtin ("__builtin_aarch64_memtag_"#N, \
- T, AARCH64_MEMTAG_BUILTIN_##F); \
+ = aarch64_general_simulate_builtin ("__arm_mte_"#N, T, \
+ AARCH64_MEMTAG_BUILTIN_##F); \
aarch64_memtag_builtin_data[AARCH64_MEMTAG_BUILTIN_##F - \
AARCH64_MEMTAG_BUILTIN_START - 1] = \
{T, CODE_FOR_##I};
fntype = build_function_type_list (ptr_type_node, ptr_type_node,
uint64_type_node, NULL);
- AARCH64_INIT_MEMTAG_BUILTINS_DECL (IRG, irg, irg, fntype);
+ AARCH64_INIT_MEMTAG_BUILTINS_DECL (IRG, create_random_tag, irg, fntype);
fntype = build_function_type_list (uint64_type_node, ptr_type_node,
uint64_type_node, NULL);
- AARCH64_INIT_MEMTAG_BUILTINS_DECL (GMI, gmi, gmi, fntype);
+ AARCH64_INIT_MEMTAG_BUILTINS_DECL (GMI, exclude_tag, gmi, fntype);
fntype = build_function_type_list (ptrdiff_type_node, ptr_type_node,
ptr_type_node, NULL);
- AARCH64_INIT_MEMTAG_BUILTINS_DECL (SUBP, subp, subp, fntype);
+ AARCH64_INIT_MEMTAG_BUILTINS_DECL (SUBP, ptrdiff, subp, fntype);
fntype = build_function_type_list (ptr_type_node, ptr_type_node,
unsigned_type_node, NULL);
- AARCH64_INIT_MEMTAG_BUILTINS_DECL (INC_TAG, inc_tag, addg, fntype);
+ AARCH64_INIT_MEMTAG_BUILTINS_DECL (INC_TAG, increment_tag, addg, fntype);
fntype = build_function_type_list (void_type_node, ptr_type_node, NULL);
AARCH64_INIT_MEMTAG_BUILTINS_DECL (SET_TAG, set_tag, stg, fntype);
@@ -2065,6 +2065,7 @@ handle_arm_acle_h (void)
if (TARGET_LS64)
aarch64_init_ls64_builtins ();
aarch64_init_tme_builtins ();
+ aarch64_init_memtag_builtins ();
}
/* Initialize fpsr fpcr getters and setters. */
@@ -2157,9 +2158,6 @@ aarch64_general_init_builtins (void)
if (!TARGET_ILP32)
aarch64_init_pauth_hint_builtins ();
- if (TARGET_MEMTAG)
- aarch64_init_memtag_builtins ();
-
if (in_lto_p)
handle_arm_acle_h ();
}
@@ -2316,7 +2314,12 @@ aarch64_general_check_builtin_call (location_t location, vec<location_t>,
default:
break;
}
- /* Default behavior. */
+
+ if (code >= AARCH64_MEMTAG_BUILTIN_START
+ && code <= AARCH64_MEMTAG_BUILTIN_END)
+ return aarch64_check_required_extensions (location, decl,
+ AARCH64_FL_MEMTAG);
+
return true;
}
diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index 2d84ab1bd3f3..ab0432679130 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -287,29 +287,6 @@ __rndrrs (uint64_t *__res)
#pragma GCC pop_options
-#pragma GCC push_options
-#pragma GCC target ("+nothing+memtag")
-
-#define __arm_mte_create_random_tag(__ptr, __u64_mask) \
- __builtin_aarch64_memtag_irg(__ptr, __u64_mask)
-
-#define __arm_mte_exclude_tag(__ptr, __u64_excluded) \
- __builtin_aarch64_memtag_gmi(__ptr, __u64_excluded)
-
-#define __arm_mte_ptrdiff(__ptr_a, __ptr_b) \
- __builtin_aarch64_memtag_subp(__ptr_a, __ptr_b)
-
-#define __arm_mte_increment_tag(__ptr, __u_offset) \
- __builtin_aarch64_memtag_inc_tag(__ptr, __u_offset)
-
-#define __arm_mte_set_tag(__tagged_address) \
- __builtin_aarch64_memtag_set_tag(__tagged_address)
-
-#define __arm_mte_get_tag(__address) \
- __builtin_aarch64_memtag_get_tag(__address)
-
-#pragma GCC pop_options
-
#define __arm_rsr(__regname) \
__builtin_aarch64_rsr (__regname)
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-1.c b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-1.c
new file mode 100644
index 000000000000..4a34c37f44fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.5-a" } */
+
+#include <arm_acle.h>
+
+void foo (int * p)
+{
+ __arm_mte_set_tag (p); /* { dg-error {ACLE function '__arm_mte_set_tag' requires ISA extension 'memtag'} } */
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-2.c b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-2.c
new file mode 100644
index 000000000000..bf06b284dadd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.5-a" } */
+
+#include <arm_acle.h>
+
+#pragma GCC target("arch=armv8.5-a+memtag")
+void foo (int * p)
+{
+ __arm_mte_set_tag (p);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-3.c b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-3.c
new file mode 100644
index 000000000000..1f4ffa454a76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.5-a+memtag -mgeneral-regs-only" } */
+
+#include <arm_acle.h>
+
+void foo (int * p)
+{
+ __arm_mte_set_tag (p);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-4.c b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-4.c
new file mode 100644
index 000000000000..a1cd45ec79d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.5-a+memtag" } */
+
+#include <arm_acle.h>
+
+#pragma GCC target("arch=armv8.5-a")
+void foo (int * p)
+{
+ __arm_mte_set_tag (p); /* { dg-error {ACLE function '__arm_mte_set_tag' requires ISA extension 'memtag'} } */
+}
--
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