From 52a6b06c26346cfb6972252ef547720b431844e6 Mon Sep 17 00:00:00 2001
From: Uros Bizjak <ubizjak@gmail.com>
Date: Wed, 29 Dec 2021 09:34:32 +0100
Subject: [PATCH] i386: Robustify some expanders w.r.t. paradoxical SUBREGs
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lowpart_subreg might fail in some cases when trying to create paradoxical
SUBREGs. Use force_reg on input operand, use new temporary output operand
and emit move into the destination afterwards.
Also, replace simplify_gen_subreg (Mx, op, My, 0)
with equivalent lowpart_subreg (Mx, op, My).
2021-12-29 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
* config/i386/sse.md (vec_pack<floatprefix>_float_<mode>):
Perform gen_avx512dq_float<floatunssuffix>v2div2sf2 into a
pseudo and emit move insn into operands[0].
(fix<fixunssuffix>_truncv2sfv2di2): Use lowpart_subreg
instead of simplify_gen_subreg.
(trunc<mode><pmov_dst_3_lower>2): Perform
gen_avx512vl_truncate<mode>v<ssescalarnum>qi2 into a
pseudo and emit move insn into operands[0].
(trunc<mode><pmov_dst_4_lower>2): Perform
gen_avx512vl_truncate<mode>v<ssescalarnum>hi2 into a
pseudo and emit move insn into operands[0].
(truncv2div2si2): Perform gen_avx512vl_truncatev2div2si2 into a
pseudo and emit move insn into operands[0].
(truncv8div8qi2): Perform gen_avx512f_truncatev8div16qi2 into a
pseudo and emit move insn into operands[0].
(<any_extend:insn>v8qiv8hi2): Use lowpart_subreg
instead of simplify_gen_subreg.
(<any_extend:insn>v8qiv8si2): Ditto.
(<any_extend:insn>v4qiv4si2): Ditto.
(<any_extend:insn>v4hiv4si2): Ditto.
(<any_extend:insn>v8qiv8di2): Ditto.
(<any_extend:insn>v4qiv4di2): Ditto.
(<any_extend:insn>v2qiv2di2): Ditto.
(<any_extend:insn>v4hiv4di2): Ditto.
(<any_extend:insn>v2hiv2di2): Ditto.
(<any_extend:insn>v2siv2di2): Ditto.
---
gcc/config/i386/sse.md | 115 +++++++++++++++++++++++------------------
1 file changed, 65 insertions(+), 50 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 69c754751a8f..0997d9edf9db 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8115,9 +8115,12 @@
(any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand")))]
"TARGET_AVX512DQ && TARGET_AVX512VL"
{
- operands[0] = simplify_gen_subreg (V4SFmode, operands[0], V2SFmode, 0);
+ rtx op0 = gen_reg_rtx (V4SFmode);
+
emit_insn (gen_avx512dq_float<floatunssuffix>v2div2sf2
- (operands[0], operands[1]));
+ (op0, operands[1]));
+
+ emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
DONE;
})
@@ -8547,10 +8550,10 @@
(match_operand:V2SF 1 "register_operand")))]
"TARGET_AVX512DQ && TARGET_AVX512VL"
{
- operands[1] = force_reg (V2SFmode, operands[1]);
- operands[1] = simplify_gen_subreg (V4SFmode, operands[1], V2SFmode, 0);
+ rtx op1 = force_reg (V2SFmode, operands[1]);
+ op1 = lowpart_subreg (V4SFmode, op1, V2SFmode);
emit_insn (gen_avx512dq_fix<fixunssuffix>_truncv2sfv2di2
- (operands[0], operands[1]));
+ (operands[0], op1));
DONE;
})
@@ -13631,10 +13634,13 @@
(match_operand:PMOV_SRC_MODE_3 1 "register_operand")))]
"TARGET_AVX512VL"
{
- operands[0] = simplify_gen_subreg (V16QImode, operands[0], <pmov_dst_3>mode, 0);
- emit_insn (gen_avx512vl_truncate<mode>v<ssescalarnum>qi2 (operands[0],
- operands[1],
- CONST0_RTX (<pmov_dst_zeroed_3>mode)));
+ rtx op0 = gen_reg_rtx (V16QImode);
+
+ emit_insn (gen_avx512vl_truncate<mode>v<ssescalarnum>qi2
+ (op0, operands[1], CONST0_RTX (<pmov_dst_zeroed_3>mode)));
+
+ emit_move_insn (operands[0],
+ lowpart_subreg (<pmov_dst_3>mode, op0, V16QImode));
DONE;
})
@@ -14006,12 +14012,14 @@
(match_operand:PMOV_SRC_MODE_4 1 "register_operand")))]
"TARGET_AVX512VL"
{
- operands[0] = simplify_gen_subreg (V8HImode, operands[0], <pmov_dst_4>mode, 0);
- emit_insn (gen_avx512vl_truncate<mode>v<ssescalarnum>hi2 (operands[0],
- operands[1],
- CONST0_RTX (<pmov_dst_zeroed_4>mode)));
- DONE;
+ rtx op0 = gen_reg_rtx (V8HImode);
+
+ emit_insn (gen_avx512vl_truncate<mode>v<ssescalarnum>hi2
+ (op0, operands[1], CONST0_RTX (<pmov_dst_zeroed_4>mode)));
+ emit_move_insn (operands[0],
+ lowpart_subreg (<pmov_dst_4>mode, op0, V8HImode));
+ DONE;
})
(define_insn "avx512vl_<code><mode>v<ssescalarnum>hi2"
@@ -14251,10 +14259,13 @@
(match_operand:V2DI 1 "register_operand")))]
"TARGET_AVX512VL"
{
- operands[0] = simplify_gen_subreg (V4SImode, operands[0], V2SImode, 0);
- emit_insn (gen_avx512vl_truncatev2div2si2 (operands[0],
- operands[1],
- CONST0_RTX (V2SImode)));
+ rtx op0 = gen_reg_rtx (V4SImode);
+
+ emit_insn (gen_avx512vl_truncatev2div2si2
+ (op0, operands[1], CONST0_RTX (V2SImode)));
+
+ emit_move_insn (operands[0],
+ lowpart_subreg (V2SImode, op0, V4SImode));
DONE;
})
@@ -14389,8 +14400,12 @@
(match_operand:V8DI 1 "register_operand")))]
"TARGET_AVX512F"
{
- operands[0] = simplify_gen_subreg (V16QImode, operands[0], V8QImode, 0);
- emit_insn (gen_avx512f_truncatev8div16qi2 (operands[0], operands[1]));
+ rtx op0 = gen_reg_rtx (V16QImode);
+
+ emit_insn (gen_avx512f_truncatev8div16qi2 (op0, operands[1]));
+
+ emit_move_insn (operands[0],
+ lowpart_subreg (V8QImode, op0, V16QImode));
DONE;
})
@@ -21625,9 +21640,9 @@
{
if (!MEM_P (operands[1]))
{
- operands[1] = force_reg (V8QImode, operands[1]);
- operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0);
- emit_insn (gen_sse4_1_<code>v8qiv8hi2 (operands[0], operands[1]));
+ rtx op1 = force_reg (V8QImode, operands[1]);
+ op1 = lowpart_subreg (V16QImode, op1, V8QImode);
+ emit_insn (gen_sse4_1_<code>v8qiv8hi2 (operands[0], op1));
DONE;
}
})
@@ -21703,9 +21718,9 @@
{
if (!MEM_P (operands[1]))
{
- operands[1] = force_reg (V8QImode, operands[1]);
- operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0);
- emit_insn (gen_avx2_<code>v8qiv8si2 (operands[0], operands[1]));
+ rtx op1 = force_reg (V8QImode, operands[1]);
+ op1 = lowpart_subreg (V16QImode, op1, V8QImode);
+ emit_insn (gen_avx2_<code>v8qiv8si2 (operands[0], op1));
DONE;
}
})
@@ -21767,9 +21782,9 @@
{
if (!MEM_P (operands[1]))
{
- operands[1] = force_reg (V4QImode, operands[1]);
- operands[1] = simplify_gen_subreg (V16QImode, operands[1], V4QImode, 0);
- emit_insn (gen_sse4_1_<code>v4qiv4si2 (operands[0], operands[1]));
+ rtx op1 = force_reg (V4QImode, operands[1]);
+ op1 = lowpart_subreg (V16QImode, op1, V4QImode);
+ emit_insn (gen_sse4_1_<code>v4qiv4si2 (operands[0], op1));
DONE;
}
})
@@ -21935,9 +21950,9 @@
{
if (!MEM_P (operands[1]))
{
- operands[1] = force_reg (V4HImode, operands[1]);
- operands[1] = simplify_gen_subreg (V8HImode, operands[1], V4HImode, 0);
- emit_insn (gen_sse4_1_<code>v4hiv4si2 (operands[0], operands[1]));
+ rtx op1 = force_reg (V4HImode, operands[1]);
+ op1 = lowpart_subreg (V8HImode, op1, V4HImode);
+ emit_insn (gen_sse4_1_<code>v4hiv4si2 (operands[0], op1));
DONE;
}
})
@@ -22056,9 +22071,9 @@
{
if (!MEM_P (operands[1]))
{
- operands[1] = force_reg (V8QImode, operands[1]);
- operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0);
- emit_insn (gen_avx512f_<code>v8qiv8di2 (operands[0], operands[1]));
+ rtx op1 = force_reg (V8QImode, operands[1]);
+ op1 = lowpart_subreg (V16QImode, op1, V8QImode);
+ emit_insn (gen_avx512f_<code>v8qiv8di2 (operands[0], op1));
DONE;
}
})
@@ -22118,9 +22133,9 @@
{
if (!MEM_P (operands[1]))
{
- operands[1] = force_reg (V4QImode, operands[1]);
- operands[1] = simplify_gen_subreg (V16QImode, operands[1], V4QImode, 0);
- emit_insn (gen_avx2_<code>v4qiv4di2 (operands[0], operands[1]));
+ rtx op1 = force_reg (V4QImode, operands[1]);
+ op1 = lowpart_subreg (V16QImode, operands[1], V4QImode);
+ emit_insn (gen_avx2_<code>v4qiv4di2 (operands[0], op1));
DONE;
}
})
@@ -22145,9 +22160,9 @@
(match_operand:V2QI 1 "register_operand")))]
"TARGET_SSE4_1"
{
- operands[1] = force_reg (V2QImode, operands[1]);
- operands[1] = simplify_gen_subreg (V16QImode, operands[1], V2QImode, 0);
- emit_insn (gen_sse4_1_<code>v2qiv2di2 (operands[0], operands[1]));
+ rtx op1 = force_reg (V2QImode, operands[1]);
+ op1 = lowpart_subreg (V16QImode, op1, V2QImode);
+ emit_insn (gen_sse4_1_<code>v2qiv2di2 (operands[0], op1));
DONE;
})
@@ -22218,9 +22233,9 @@
{
if (!MEM_P (operands[1]))
{
- operands[1] = force_reg (V4HImode, operands[1]);
- operands[1] = simplify_gen_subreg (V8HImode, operands[1], V4HImode, 0);
- emit_insn (gen_avx2_<code>v4hiv4di2 (operands[0], operands[1]));
+ rtx op1 = force_reg (V4HImode, operands[1]);
+ op1 = lowpart_subreg (V8HImode, op1, V4HImode);
+ emit_insn (gen_avx2_<code>v4hiv4di2 (operands[0], op1));
DONE;
}
})
@@ -22280,9 +22295,9 @@
{
if (!MEM_P (operands[1]))
{
- operands[1] = force_reg (V2HImode, operands[1]);
- operands[1] = simplify_gen_subreg (V8HImode, operands[1], V2HImode, 0);
- emit_insn (gen_sse4_1_<code>v2hiv2di2 (operands[0], operands[1]));
+ rtx op1 = force_reg (V2HImode, operands[1]);
+ op1 = lowpart_subreg (V8HImode, op1, V2HImode);
+ emit_insn (gen_sse4_1_<code>v2hiv2di2 (operands[0], op1));
DONE;
}
})
@@ -22497,9 +22512,9 @@
{
if (!MEM_P (operands[1]))
{
- operands[1] = force_reg (V2SImode, operands[1]);
- operands[1] = simplify_gen_subreg (V4SImode, operands[1], V2SImode, 0);
- emit_insn (gen_sse4_1_<code>v2siv2di2 (operands[0], operands[1]));
+ rtx op1 = force_reg (V2SImode, operands[1]);
+ op1 = lowpart_subreg (V4SImode, op1, V2SImode);
+ emit_insn (gen_sse4_1_<code>v2siv2di2 (operands[0], op1));
DONE;
}
})
--
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