From 5329b94188206e9f8c96d9a63931c415fa5d39d7 Mon Sep 17 00:00:00 2001
From: Andrew Pinski <quic_apinski@quicinc.com>
Date: Wed, 14 Feb 2024 14:29:22 -0800
Subject: [PATCH] doc: Add documentation of which operand matches the mode of
the standard pattern name [PR113508]
In some of the standard pattern names, it is not obvious which mode is being used in the pattern
name. Is it operand 0, 1, or 2? Is it the wider mode or the narrower mode?
This fixes that so there is no confusion by adding a sentence to some of them.
Built the documentation to make sure that it builds.
gcc/ChangeLog:
PR middle-end/113508
* doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
Add sentence about what the mode m is.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
---
gcc/doc/md.texi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 274dd03d4191..33b37e79cd4a 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -5746,6 +5746,7 @@ Operand 1 and operand 2 are of the same mode. Their
product, which is of a wider mode, is computed and added to operand 3.
Operand 3 is of a mode equal or wider than the mode of the product. The
result is placed in operand 0, which is of the same mode as operand 3.
+@var{m} is the mode of operand 1 and operand 2.
Semantically the expressions perform the multiplication in the following signs
@@ -5763,6 +5764,7 @@ Operand 1 and operand 2 are of the same mode. Their
product, which is of a wider mode, is computed and added to operand 3.
Operand 3 is of a mode equal or wider than the mode of the product. The
result is placed in operand 0, which is of the same mode as operand 3.
+@var{m} is the mode of operand 1 and operand 2.
Semantically the expressions perform the multiplication in the following signs
@@ -5779,6 +5781,7 @@ Operand 1 must be unsigned and operand 2 signed. Their
product, which is of a wider mode, is computed and added to operand 3.
Operand 3 is of a mode equal or wider than the mode of the product. The
result is placed in operand 0, which is of the same mode as operand 3.
+@var{m} is the mode of operand 1 and operand 2.
Semantically the expressions perform the multiplication in the following signs
@@ -5797,6 +5800,7 @@ Operand 1 and operand 2 are of the same mode. Their absolute difference, which
is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
equal or wider than the mode of the absolute difference. The result is placed
in operand 0, which is of the same mode as operand 3.
+@var{m} is the mode of operand 1 and operand 2.
@cindex @code{widen_ssum@var{m}3} instruction pattern
@cindex @code{widen_usum@var{m}3} instruction pattern
@@ -5806,6 +5810,7 @@ Operands 0 and 2 are of the same mode, which is wider than the mode of
operand 1. Add operand 1 to operand 2 and place the widened result in
operand 0. (This is used express accumulation of elements into an accumulator
of a wider mode.)
+@var{m} is the mode of operand 1.
@cindex @code{smulhs@var{m}3} instruction pattern
@cindex @code{umulhs@var{m}3} instruction pattern
@@ -5819,6 +5824,8 @@ op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1));
@end smallexample
where the sign of @samp{narrow} determines whether this is a signed
or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
+@var{m} is the mode for all 3 operands (narrow). The wide mode is not specified
+and is defined to fit the whole multiply.
@cindex @code{smulhrs@var{m}3} instruction pattern
@cindex @code{umulhrs@var{m}3} instruction pattern
@@ -5833,6 +5840,8 @@ op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1);
@end smallexample
where the sign of @samp{narrow} determines whether this is a signed
or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
+@var{m} is the mode for all 3 operands (narrow). The wide mode is not specified
+and is defined to fit the whole multiply.
@cindex @code{sdiv_pow2@var{m}3} instruction pattern
@cindex @code{sdiv_pow2@var{m}3} instruction pattern
--
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