From 58b78cf068b3b24c11d7812a5f4de865e9cdb8b4 Mon Sep 17 00:00:00 2001
From: Oleg Endo <olegendo@gcc.gnu.org>
Date: Sun, 21 Jul 2024 14:11:21 +0900
Subject: [PATCH] SH: Fix outage caused by recently added 2nd combine pass
after reg alloc
I've also confirmed on the CSiBE set that the secondary combine pass is
actually beneficial on SH. It does result in some code size reductions.
gcc/CHangeLog:
* config/sh/sh.md (mov_neg_si_t): Allow insn and split after
register allocation.
(*treg_noop_move): New insn.
---
gcc/config/sh/sh.md | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 3e978254ab0c..7eee12ca6b8a 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -8408,7 +8408,7 @@
gcc_assert (t_reg_operand (operands[1], VOIDmode));
return "subc %0,%0";
}
- "&& can_create_pseudo_p () && !t_reg_operand (operands[1], VOIDmode)"
+ "&& !t_reg_operand (operands[1], VOIDmode)"
[(const_int 0)]
{
sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
@@ -8421,6 +8421,14 @@
}
[(set_attr "type" "arith")])
+;; no-op T bit move which can result from other optimizations.
+(define_insn_and_split "*treg_noop_move"
+ [(set (reg:SI T_REG) (reg:SI T_REG))]
+ "TARGET_SH1"
+ "#"
+ "&& 1"
+ [(const_int 0)])
+
;; Invert the T bit.
;; On SH2A we can use the nott insn. On anything else this must be done with
;; multiple insns like:
--
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