diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 50232bf9b86de30ddc68a11719d849d47adb31c9..3fa27b93de9694178d930ae6a42374b5ba1a9eca 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2023-08-23  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/111010
+	* config/i386/i386.md (*concat<any_or_plus:mode><dwi>3_3):
+	Disable (=&r,m,m) alternative for 32-bit targets.
+	(*concat<any_or_plus:mode><dwi>3_4): Ditto.
+
 2023-08-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 
 	* config/riscv/t-riscv: Add riscv-vsetvl.def
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 47b00c6c0bd5f37f1a37ce14190bbb7e0d8ffb8e..d736aa1f38ab24234f72e6aea22f709a38176647 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230823
+20230824