From 62e7c496696eb68186616a2fa3654a876d21d695 Mon Sep 17 00:00:00 2001
From: Dimitar Dimitrov <dimitar@dinux.eu>
Date: Mon, 25 Nov 2024 20:48:00 +0200
Subject: [PATCH] testsuite: RISC-V: Skip V and Zvbb tests for ILP32E/ILP64E
ABIs
Some tests add options for V and Zvbb extensions, but those extensions
are not compatible with the E ABI variants. This leads to spurious test
failures when toolchain's default ABI is ILP32E or ILP64E:
spawn ... -march=rv32ecv_zvbb ...
cc1: error: ILP32E ABI does not support the 'D' extension
cc1: sorry, unimplemented: Currently the 'V' implementation requires the 'M' extension
Fix by skipping the tests when toolchain's default ABI is E variant.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vandn-1.c: Skip if default
is E ABI.
* gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vwsll-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vwsll-template.h: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/clz-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/ctz-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/popcount-3.c: Ditto.
* gcc.target/riscv/rvv/base/cmpmem-1.c: Ditto.
* gcc.target/riscv/rvv/base/cmpmem-3.c: Ditto.
* gcc.target/riscv/rvv/base/cmpmem-4.c: Ditto.
* gcc.target/riscv/rvv/base/cpymem-1.c: Ditto.
* gcc.target/riscv/rvv/base/cpymem-2.c: Ditto.
* gcc.target/riscv/rvv/base/cpymem-3.c: Ditto.
* gcc.target/riscv/rvv/base/movmem-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr115068.c: Ditto.
* gcc.target/riscv/rvv/base/setmem-1.c: Ditto.
* gcc.target/riscv/rvv/base/setmem-2.c: Ditto.
* gcc.target/riscv/rvv/base/setmem-3.c: Ditto.
* gcc.target/riscv/rvv/base/vwaddsub-1.c: Ditto.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vwsll-template.h | 2 +-
.../riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c | 2 +-
22 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
index 3bb5bf8dd5ba..dfdc64b568dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
index 55dac27697cb..1c5f6e046d02 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
index a2e5b4f5aa12..0a67db77a6ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
index 376cbaee0d51..89b7624fe9fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
index 1fd3644886ac..de5a5ed7d56a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-fno-vect-cost-model -fdump-tree-vect-details -mrvv-max-lmul=m4" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
index c27d9d399b93..483b58f8af70 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
index d5989bd5aad5..2425dc86404a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
index 1396e46ec8cc..12324f19867a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
index 116cc304da37..7e6880370e13 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
index 00b87a07fd89..6bf890998843 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvbb" } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
index 6bc8b07bc2c6..9edd6cb54ba9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
index 5ca31af90fb7..82aa30765792 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
index 5860b27a2335..e2dd6a1c45fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 81d14d836334..654c80087d24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-add-options riscv_v } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
index 7b6a429f34cf..3d79b5987fd8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
/* { dg-add-options riscv_v } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
index f07078ba6a7c..2b75b314fae7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
/* { dg-add-options riscv_v } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
index 1f148bc70528..03e633be2719 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
index 8359e81629d8..af2cba6039d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-std=gnu99" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
index 22844ff348cc..a22d366de9b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
index 838fbebadff3..a10886862b28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
index 449338197158..460a8f2c7fe9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
index 196215a1f7b7..6e027a555f37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
--
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