diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
index 8c6d8e88d1a79187a2094b46847eb484ad2b3620..4f254872e33dba6230f8fb977124ee692b8319cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
@@ -27,6 +27,22 @@
   for (int i = 0; i < SZ; i++)			\
     assert (as##TYPE[i] == 999 - VAL);
 
+#define RUN3(TYPE)				\
+  TYPE as2##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as2##TYPE[i] = i * 33 - 779;            	\
+  vsubi_##TYPE (as2##TYPE, as2##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as2##TYPE[i] == (TYPE)(-16 - (i * 33 - 779)));
+
+#define RUN4(TYPE)				\
+  TYPE as3##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as3##TYPE[i] = i * -17 + 667;            	\
+  vsubi2_##TYPE (as3##TYPE, as3##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as3##TYPE[i] == (TYPE)(15 - (i * -17 + 667)));
+
 #define RUN_ALL()	\
  RUN(int16_t, 1)	\
  RUN(uint16_t, 2)	\
@@ -39,7 +55,19 @@
  RUN2(int32_t, 9)	\
  RUN2(uint32_t, 10)	\
  RUN2(int64_t, 11)	\
- RUN2(uint64_t, 12)
+ RUN2(uint64_t, 12)	\
+ RUN3(int16_t)		\
+ RUN3(uint16_t)		\
+ RUN3(int32_t)		\
+ RUN3(uint32_t)		\
+ RUN3(int64_t)		\
+ RUN3(uint64_t)		\
+ RUN4(int16_t)		\
+ RUN4(uint16_t)		\
+ RUN4(int32_t)		\
+ RUN4(uint32_t)		\
+ RUN4(int64_t)		\
+ RUN4(uint64_t)
 
 int main ()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
index e2bdd0fe9049631c695a1aa155b66e94e7b38a26..a0d3802be653a3786500e3c7cb2ea0018f3d5fb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
@@ -4,3 +4,4 @@
 #include "vsub-template.h"
 
 /* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
index f7a2691b9f3fb5514dd876c07f54f3c18648203d..562c026a7e4fa2deede9aec7259044943aaf33e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
@@ -4,3 +4,4 @@
 #include "vsub-template.h"
 
 /* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
index 8c0a9c99217100640481ab35d3f3c4ac88730e94..47f07f134629524382cd17af0945ed004fd959e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
@@ -16,6 +16,22 @@
       dst[i] = a[i] - b;				\
   }
 
+#define TEST3_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vsubi_##TYPE (TYPE *dst, TYPE *a, int n)		\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = -16 - a[i];				\
+  }
+
+#define TEST4_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vsubi2_##TYPE (TYPE *dst, TYPE *a, int n) 	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = 15 - a[i];				\
+  }
+
 /* *int8_t not autovec currently. */
 #define TEST_ALL()	\
  TEST_TYPE(int16_t)	\
@@ -30,5 +46,17 @@
  TEST2_TYPE(uint32_t)	\
  TEST2_TYPE(int64_t)	\
  TEST2_TYPE(uint64_t)
+ TEST3_TYPE(int16_t)	\
+ TEST3_TYPE(uint16_t)	\
+ TEST3_TYPE(int32_t)	\
+ TEST3_TYPE(uint32_t)	\
+ TEST3_TYPE(int64_t)	\
+ TEST3_TYPE(uint64_t)	\
+ TEST4_TYPE(int16_t)	\
+ TEST4_TYPE(uint16_t)	\
+ TEST4_TYPE(int32_t)	\
+ TEST4_TYPE(uint32_t)	\
+ TEST4_TYPE(int64_t)	\
+ TEST4_TYPE(uint64_t)
 
 TEST_ALL()