diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 1c22f96ec26236319eeb5f5542be7a24591591b6..493d57454858f81e2f825662789cf253ffd3387d 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2089,7 +2089,7 @@
 (define_insn_and_split "reduc_plus_scal_<mode>"
   [(set (match_operand:<VEL> 0 "register_operand")
         (unspec:<VEL> [
-             (match_operand:VI 1 "register_operand")
+             (match_operand:V_VLSI 1 "register_operand")
         ] UNSPEC_REDUC_SUM))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
@@ -2104,7 +2104,7 @@
 
 (define_expand "reduc_smax_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VI 1 "register_operand")]
+   (match_operand:V_VLSI 1 "register_operand")]
   "TARGET_VECTOR"
 {
   int prec = GET_MODE_PRECISION (<VEL>mode);
@@ -2116,7 +2116,7 @@
 
 (define_expand "reduc_umax_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VI 1 "register_operand")]
+   (match_operand:V_VLSI 1 "register_operand")]
   "TARGET_VECTOR"
 {
   riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, riscv_vector::REDUCE_OP,
@@ -2126,7 +2126,7 @@
 
 (define_expand "reduc_smin_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VI 1 "register_operand")]
+   (match_operand:V_VLSI 1 "register_operand")]
   "TARGET_VECTOR"
 {
   int prec = GET_MODE_PRECISION (<VEL>mode);
@@ -2138,7 +2138,7 @@
 
 (define_expand "reduc_umin_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VI 1 "register_operand")]
+   (match_operand:V_VLSI 1 "register_operand")]
   "TARGET_VECTOR"
 {
   int prec = GET_MODE_PRECISION (<VEL>mode);
@@ -2150,7 +2150,7 @@
 
 (define_expand "reduc_and_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VI 1 "register_operand")]
+   (match_operand:V_VLSI 1 "register_operand")]
   "TARGET_VECTOR"
 {
   riscv_vector::expand_reduction (UNSPEC_REDUC_AND, riscv_vector::REDUCE_OP,
@@ -2160,7 +2160,7 @@
 
 (define_expand "reduc_ior_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VI 1 "register_operand")]
+   (match_operand:V_VLSI 1 "register_operand")]
   "TARGET_VECTOR"
 {
   riscv_vector::expand_reduction (UNSPEC_REDUC_OR, riscv_vector::REDUCE_OP,
@@ -2170,7 +2170,7 @@
 
 (define_expand "reduc_xor_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VI 1 "register_operand")]
+   (match_operand:V_VLSI 1 "register_operand")]
   "TARGET_VECTOR"
 {
   riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, riscv_vector::REDUCE_OP,
@@ -2190,7 +2190,7 @@
 (define_insn_and_split "reduc_plus_scal_<mode>"
   [(set (match_operand:<VEL> 0 "register_operand")
         (unspec:<VEL> [
-             (match_operand:VF 1 "register_operand")
+             (match_operand:V_VLSF 1 "register_operand")
         ] UNSPEC_REDUC_SUM_UNORDERED))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
@@ -2206,7 +2206,7 @@
 
 (define_expand "reduc_smax_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VF 1 "register_operand")]
+   (match_operand:V_VLSF 1 "register_operand")]
   "TARGET_VECTOR"
 {
   REAL_VALUE_TYPE rv;
@@ -2219,7 +2219,7 @@
 
 (define_expand "reduc_smin_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VF 1 "register_operand")]
+   (match_operand:V_VLSF 1 "register_operand")]
   "TARGET_VECTOR"
 {
   REAL_VALUE_TYPE rv;
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index fa9892cebc1b22863fadbb5f6b181b8f1f5d234d..0b395e65228d6f38c900caccd72debdfbcb04df1 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1300,6 +1300,86 @@
   (RVVM8SF "RVVM1SF") (RVVM4SF "RVVM1SF") (RVVM2SF "RVVM1SF") (RVVM1SF "RVVM1SF") (RVVMF2SF "RVVM1SF")
 
   (RVVM8DF "RVVM1DF") (RVVM4DF "RVVM1DF") (RVVM2DF "RVVM1DF") (RVVM1DF "RVVM1DF")
+
+  (V1QI "RVVM1QI")
+  (V2QI "RVVM1QI")
+  (V4QI "RVVM1QI")
+  (V8QI "RVVM1QI")
+  (V16QI "RVVM1QI")
+  (V32QI "RVVM1QI")
+  (V64QI "RVVM1QI")
+  (V128QI "RVVM1QI")
+  (V256QI "RVVM1QI")
+  (V512QI "RVVM1QI")
+  (V1024QI "RVVM1QI")
+  (V2048QI "RVVM1QI")
+  (V4096QI "RVVM1QI")
+  (V1HI "RVVM1HI")
+  (V2HI "RVVM1HI")
+  (V4HI "RVVM1HI")
+  (V8HI "RVVM1HI")
+  (V16HI "RVVM1HI")
+  (V32HI "RVVM1HI")
+  (V64HI "RVVM1HI")
+  (V128HI "RVVM1HI")
+  (V256HI "RVVM1HI")
+  (V512HI "RVVM1HI")
+  (V1024HI "RVVM1HI")
+  (V2048HI "RVVM1HI")
+  (V1SI "RVVM1SI")
+  (V2SI "RVVM1SI")
+  (V4SI "RVVM1SI")
+  (V8SI "RVVM1SI")
+  (V16SI "RVVM1SI")
+  (V32SI "RVVM1SI")
+  (V64SI "RVVM1SI")
+  (V128SI "RVVM1SI")
+  (V256SI "RVVM1SI")
+  (V512SI "RVVM1SI")
+  (V1024SI "RVVM1SI")
+  (V1DI "RVVM1DI")
+  (V2DI "RVVM1DI")
+  (V4DI "RVVM1DI")
+  (V8DI "RVVM1DI")
+  (V16DI "RVVM1DI")
+  (V32DI "RVVM1DI")
+  (V64DI "RVVM1DI")
+  (V128DI "RVVM1DI")
+  (V256DI "RVVM1DI")
+  (V512DI "RVVM1DI")
+  (V1HF "RVVM1HF")
+  (V2HF "RVVM1HF")
+  (V4HF "RVVM1HF")
+  (V8HF "RVVM1HF")
+  (V16HF "RVVM1HF")
+  (V32HF "RVVM1HF")
+  (V64HF "RVVM1HF")
+  (V128HF "RVVM1HF")
+  (V256HF "RVVM1HF")
+  (V512HF "RVVM1HF")
+  (V1024HF "RVVM1HF")
+  (V2048HF "RVVM1HF")
+  (V1SF "RVVM1SF")
+  (V2SF "RVVM1SF")
+  (V4SF "RVVM1SF")
+  (V8SF "RVVM1SF")
+  (V16SF "RVVM1SF")
+  (V32SF "RVVM1SF")
+  (V64SF "RVVM1SF")
+  (V128SF "RVVM1SF")
+  (V256SF "RVVM1SF")
+  (V512SF "RVVM1SF")
+  (V1024SF "RVVM1SF")
+  (V1DF "RVVM1DF")
+  (V2DF "RVVM1DF")
+  (V4DF "RVVM1DF")
+  (V8DF "RVVM1DF")
+  (V16DF "RVVM1DF")
+  (V32DF "RVVM1DF")
+  (V64DF "RVVM1DF")
+  (V128DF "RVVM1DF")
+  (V256DF "RVVM1DF")
+  (V512DF "RVVM1DF")
 ])
 
 (define_mode_attr V_EXT_LMUL1 [
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 44a344796ea7b6787871173f7ce30673a5c3b0e4..39b550c1bffe0c1c2598ffeaaa5bca575ccda3fc 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7906,7 +7906,7 @@
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	   (unspec:<V_LMUL1> [
-             (match_operand:VI            3 "register_operand"      "   vr,   vr")
+             (match_operand:V_VLSI        3 "register_operand"      "   vr,   vr")
              (match_operand:<V_LMUL1>     4 "register_operand"      "   vr,   vr")
            ] ANY_REDUC)
 	   (match_operand:<V_LMUL1>       2 "vector_merge_operand"  "   vu,    0")] UNSPEC_REDUC))]
@@ -7948,7 +7948,7 @@
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
            (unspec:<V_LMUL1> [
-             (match_operand:VF            3 "register_operand"      "   vr,   vr")
+             (match_operand:V_VLSF        3 "register_operand"      "   vr,   vr")
              (match_operand:<V_LMUL1>     4 "register_operand"      "   vr,   vr")
            ] ANY_FREDUC)
 	   (match_operand:<V_LMUL1>       2 "vector_merge_operand"  "   vu,    0")] UNSPEC_REDUC))]
@@ -7971,7 +7971,7 @@
 	     (reg:SI VTYPE_REGNUM)
 	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
            (unspec:<V_LMUL1> [
-             (match_operand:VF            3 "register_operand"      "   vr,   vr")
+             (match_operand:V_VLSF        3 "register_operand"      "   vr,   vr")
              (match_operand:<V_LMUL1>     4 "register_operand"      "   vr,   vr")
            ] ANY_FREDUC_SUM)
 	   (match_operand:<V_LMUL1>       2 "vector_merge_operand"  "   vu,    0")] UNSPEC_REDUC))]