From 7d81a56745d42ec9ec6dc044135d458978722b59 Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu <claziss@synopsys.com>
Date: Thu, 28 Apr 2016 14:52:04 +0200
Subject: [PATCH] [ARC] Fix FPX/FPUDA code gen when compiling for big-endian.
gcc/
2016-04-28 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_process_double_reg_moves): Fix for
big-endian compilation.
(arc_rtx_costs): Fix high/low naming.
* config/arc/arc.md (addf3): Likewise.
(subdf3): Likewise.
(muldf3): Likewise.
From-SVN: r235567
---
gcc/ChangeLog | 8 ++++++++
gcc/config/arc/arc.c | 21 ++++++++++++---------
gcc/config/arc/arc.md | 18 +++++++++---------
3 files changed, 29 insertions(+), 18 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f8bbb313a0a4..39443cc559c0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2016-04-28 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.c (arc_process_double_reg_moves): Fix for
+ big-endian compilation.
+ * config/arc/arc.md (addf3): Likewise.
+ (subdf3): Likewise.
+ (muldf3): Likewise.
+
2016-04-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/70840
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index d40d54deb34a..e7067374e465 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -4426,17 +4426,16 @@ arc_rtx_costs (rtx x, machine_mode mode, int outer_code,
case CONST_DOUBLE:
{
- rtx high, low;
+ rtx first, second;
if (TARGET_DPFP)
{
*total = COSTS_N_INSNS (1);
return true;
}
- /* FIXME: correct the order of high,low */
- split_double (x, &high, &low);
- *total = COSTS_N_INSNS (!SMALL_INT (INTVAL (high))
- + !SMALL_INT (INTVAL (low)));
+ split_double (x, &first, &second);
+ *total = COSTS_N_INSNS (!SMALL_INT (INTVAL (first))
+ + !SMALL_INT (INTVAL (second)));
return true;
}
@@ -8928,8 +8927,10 @@ arc_process_double_reg_moves (rtx *operands)
{
/* When we have 'mov D, r' or 'mov D, D' then get the target
register pair for use with LR insn. */
- rtx destHigh = simplify_gen_subreg(SImode, dest, DFmode, 4);
- rtx destLow = simplify_gen_subreg(SImode, dest, DFmode, 0);
+ rtx destHigh = simplify_gen_subreg (SImode, dest, DFmode,
+ TARGET_BIG_ENDIAN ? 0 : 4);
+ rtx destLow = simplify_gen_subreg (SImode, dest, DFmode,
+ TARGET_BIG_ENDIAN ? 4 : 0);
/* Produce the two LR insns to get the high and low parts. */
emit_insn (gen_rtx_SET (destHigh,
@@ -8946,8 +8947,10 @@ arc_process_double_reg_moves (rtx *operands)
{
/* When we have 'mov r, D' or 'mov D, D' and we have access to the
LR insn get the target register pair. */
- rtx srcHigh = simplify_gen_subreg(SImode, src, DFmode, 4);
- rtx srcLow = simplify_gen_subreg(SImode, src, DFmode, 0);
+ rtx srcHigh = simplify_gen_subreg (SImode, src, DFmode,
+ TARGET_BIG_ENDIAN ? 0 : 4);
+ rtx srcLow = simplify_gen_subreg (SImode, src, DFmode,
+ TARGET_BIG_ENDIAN ? 4 : 0);
emit_insn (gen_rtx_UNSPEC_VOLATILE (Pmode,
gen_rtvec (3, dest, srcHigh, srcLow),
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index a58b491355a9..8ec0ce0427ba 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -5752,9 +5752,9 @@
{
if (GET_CODE (operands[2]) == CONST_DOUBLE)
{
- rtx high, low, tmp;
- split_double (operands[2], &low, &high);
- tmp = force_reg (SImode, high);
+ rtx first, second, tmp;
+ split_double (operands[2], &first, &second);
+ tmp = force_reg (SImode, TARGET_BIG_ENDIAN ? first : second);
emit_insn (gen_adddf3_insn (operands[0], operands[1],
operands[2], tmp, const0_rtx));
}
@@ -5789,10 +5789,10 @@
if ((GET_CODE (operands[1]) == CONST_DOUBLE)
|| GET_CODE (operands[2]) == CONST_DOUBLE)
{
- rtx high, low, tmp;
+ rtx first, second, tmp;
int const_index = ((GET_CODE (operands[1]) == CONST_DOUBLE) ? 1 : 2);
- split_double (operands[const_index], &low, &high);
- tmp = force_reg (SImode, high);
+ split_double (operands[const_index], &first, &second);
+ tmp = force_reg (SImode, TARGET_BIG_ENDIAN ? first : second);
emit_insn (gen_subdf3_insn (operands[0], operands[1],
operands[2], tmp, const0_rtx));
}
@@ -5824,9 +5824,9 @@
{
if (GET_CODE (operands[2]) == CONST_DOUBLE)
{
- rtx high, low, tmp;
- split_double (operands[2], &low, &high);
- tmp = force_reg (SImode, high);
+ rtx first, second, tmp;
+ split_double (operands[2], &first, &second);
+ tmp = force_reg (SImode, TARGET_BIG_ENDIAN ? first : second);
emit_insn (gen_muldf3_insn (operands[0], operands[1],
operands[2], tmp, const0_rtx));
}
--
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