From 84be603271fc03e8b251ebb930b8cf86b9d00767 Mon Sep 17 00:00:00 2001
From: Alan Lawrence <alan.lawrence@arm.com>
Date: Fri, 19 Dec 2014 17:59:23 +0000
Subject: [PATCH] [AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants
for BIC,ORN,EON
gcc/:
* config/aarch64/aarch64.c (<LOGICAL:optab>_one_cmpl<mode>3):
Reparameterize to...
(<NLOGICAL:optab>_one_cmpl<mode>3): with extra SIMD-register variant.
(xor_one_cmpl<mode>3): New define_insn_and_split.
* config/aarch64/iterators.md (NLOGICAL): New define_code_iterator.
gcc/testsuite/:
* gcc.target/aarch64/eon_1.c: New test.
From-SVN: r218961
---
gcc/ChangeLog | 9 ++++++
gcc/config/aarch64/aarch64.md | 36 +++++++++++++++++-----
gcc/config/aarch64/iterators.md | 3 ++
gcc/testsuite/ChangeLog | 4 +++
gcc/testsuite/gcc.target/aarch64/eon_1.c | 39 ++++++++++++++++++++++++
5 files changed, 84 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/eon_1.c
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 10b5538cd601..e5733ae9c881 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2014-12-19 Alan Lawrence <alan.lawrence@arm.com>
+
+ * config/aarch64/aarch64.c (<LOGICAL:optab>_one_cmpl<mode>3):
+ Reparameterize to...
+ (<NLOGICAL:optab>_one_cmpl<mode>3): with extra SIMD-register variant.
+ (xor_one_cmpl<mode>3): New define_insn_and_split.
+
+ * config/aarch64/iterators.md (NLOGICAL): New define_code_iterator.
+
2014-12-19 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64.md (<optab><mode>3, one_cmpl<mode>2):
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index bc9138d6cf93..7b05359ef6c8 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3015,14 +3015,36 @@
[(set_attr "type" "logic_shift_imm")]
)
-(define_insn "*<LOGICAL:optab>_one_cmpl<mode>3"
- [(set (match_operand:GPI 0 "register_operand" "=r")
- (LOGICAL:GPI (not:GPI
- (match_operand:GPI 1 "register_operand" "r"))
- (match_operand:GPI 2 "register_operand" "r")))]
+;; Binary logical operators negating one operand, i.e. (a & !b), (a | !b).
+
+(define_insn "*<NLOGICAL:optab>_one_cmpl<mode>3"
+ [(set (match_operand:GPI 0 "register_operand" "=r,w")
+ (NLOGICAL:GPI (not:GPI (match_operand:GPI 1 "register_operand" "r,w"))
+ (match_operand:GPI 2 "register_operand" "r,w")))]
+ ""
+ "@
+ <NLOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1
+ <NLOGICAL:nlogical>\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
+ [(set_attr "type" "logic_reg,neon_logic")
+ (set_attr "simd" "*,yes")]
+)
+
+;; (xor (not a) b) is simplify_rtx-ed down to (not (xor a b)).
+;; eon does not operate on SIMD registers so the vector variant must be split.
+(define_insn_and_split "*xor_one_cmpl<mode>3"
+ [(set (match_operand:GPI 0 "register_operand" "=r,w")
+ (not:GPI (xor:GPI (match_operand:GPI 1 "register_operand" "r,?w")
+ (match_operand:GPI 2 "register_operand" "r,w"))))]
+ ""
+ "eon\\t%<w>0, %<w>1, %<w>2" ;; For GPR registers (only).
+ "reload_completed && (which_alternative == 1)" ;; For SIMD registers.
+ [(set (match_operand:GPI 0 "register_operand" "=w")
+ (xor:GPI (match_operand:GPI 1 "register_operand" "w")
+ (match_operand:GPI 2 "register_operand" "w")))
+ (set (match_dup 0) (not:GPI (match_dup 0)))]
""
- "<LOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1"
- [(set_attr "type" "logic_reg")]
+ [(set_attr "type" "logic_reg,multiple")
+ (set_attr "simd" "*,yes")]
)
(define_insn "*and_one_cmpl<mode>3_compare0"
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 26e3ebcbcabb..fe9fa97b9989 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -665,6 +665,9 @@
;; Code iterator for logical operations
(define_code_iterator LOGICAL [and ior xor])
+;; Code iterator for logical operations whose :nlogical works on SIMD registers.
+(define_code_iterator NLOGICAL [and ior])
+
;; Code iterator for sign/zero extension
(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 39f8ad2358bf..291de7744a40 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2014-12-19 Alan Lawrence <alan.lawrence@arm.com>
+
+ * gcc.target/aarch64/eon_1.c: New test.
+
2014-12-19 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/60493
diff --git a/gcc/testsuite/gcc.target/aarch64/eon_1.c b/gcc/testsuite/gcc.target/aarch64/eon_1.c
new file mode 100644
index 000000000000..dcdf3b4d052e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/eon_1.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "\tf?mov\t" } } */
+
+typedef long long int64_t;
+typedef int64_t int64x1_t __attribute__ ((__vector_size__ (8)));
+
+/* { dg-final { scan-assembler-times "\\teon\\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 1 } } */
+
+int64_t
+test_eon (int64_t a, int64_t b)
+{
+ return a ^ ~b;
+}
+
+/* { dg-final { scan-assembler-times "\\tmvn\\tx\[0-9\]+, x\[0-9\]+" 1 } } */
+int64_t
+test_not (int64_t a)
+{
+ return ~a;
+}
+
+/* There is no eon for SIMD regs; we prefer eor+mvn to mov+mov+eon+mov. */
+
+/* { dg-final { scan-assembler-times "\\teor\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
+/* { dg-final { scan-assembler-times "\\tmvn\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 2 } } */
+int64x1_t
+test_vec_eon (int64x1_t a, int64x1_t b)
+{
+ return a ^ ~b;
+}
+
+int64x1_t
+test_vec_not (int64x1_t a)
+{
+ return ~a;
+}
+
--
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