From 8eb1e39441723b0c38b13d300912a281b41fbd80 Mon Sep 17 00:00:00 2001 From: GCC Administrator <gccadmin@gcc.gnu.org> Date: Sun, 30 Apr 2023 00:16:33 +0000 Subject: [PATCH] Daily bump. --- gcc/ChangeLog | 46 +++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 22 ++++++++++++++++++++ 3 files changed, 69 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 61582da8a41b..32c66de7fb9c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,49 @@ +2023-04-29 Hans-Peter Nilsson <hp@axis.com> + + * reload1.cc (emit_insn_if_valid_for_reload_1): Rename from + emit_insn_if_valid_for_reload. + (emit_insn_if_valid_for_reload): Call new helper, and if a SET fails + to be recognized, also try emitting a parallel that clobbers + TARGET_FLAGS_REGNUM, as applicable. + +2023-04-29 Roger Sayle <roger@nextmovesoftware.com> + + * config/stormy16/stormy16.md (neghi2): Convert from a define_expand + to a define_insn. + (*rotatehi_1): New define_insn for efficient 2 insn sequence. + (*rotatehi_8, *rotaterthi_8): New define_insn to emit a swpb. + +2023-04-29 Roger Sayle <roger@nextmovesoftware.com> + + * config/stormy16/stormy16.md (any_lshift): New code iterator. + (any_or_plus): Likewise. + (any_rotate): Likewise. + (*<any_lshift>_and_internal): New define_insn_and_split to + recognize a logical shift followed by an AND, and split it + again after reload. + (*swpn): New define_insn matching xstormy16's swpn. + (*swpn_zext): New define_insn recognizing swpn followed by + zero_extendqihi2, i.e. with the high byte set to zero. + (*swpn_sext): Likewise, for swpn followed by cbw. + (*swpn_sext_2): Likewise, for an alternate RTL form. + (*swpn_zext_ior): A pre-reload splitter so that an swpn+zext+ior + sequence is split in the correct place to recognize the *swpn_zext + followed by any_or_plus (ior, xor or plus) instruction. + +2023-04-29 Mikael Pettersson <mikpelinux@gmail.com> + + PR target/105525 + * config.gcc (vax-*-linux*): Add glibc-stdint.h. + (lm32-*-uclinux*): Likewise. + +2023-04-29 Fei Gao <gaofei@eswincomputing.com> + + * config/riscv/riscv.cc (riscv_avoid_save_libcall): helper function + for riscv_use_save_libcall. + (riscv_use_save_libcall): call riscv_avoid_save_libcall. + (riscv_compute_frame_info): restructure to decouple stack allocation + for rv32e w/o save-restore. + 2023-04-28 Eugene Rozenfeld <erozen@microsoft.com> * doc/install.texi: Fix documentation typo diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 24dd3ed9702e..8de8e66b47cd 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20230429 +20230430 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3093d04f9529..85d52f2a9f76 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,25 @@ +2023-04-29 Roger Sayle <roger@nextmovesoftware.com> + + * gcc.target/xstormy16/neghi2.c: New test case. + * gcc.target/xstormy16/rotatehi-1.c: Likewise. + +2023-04-29 Roger Sayle <roger@nextmovesoftware.com> + + * gcc.target/xstormy16/swpn-1.c: New QImode test case. + * gcc.target/xstormy16/swpn-2.c: New zero_extend test case. + * gcc.target/xstormy16/swpn-3.c: New sign_extend test case. + * gcc.target/xstormy16/swpn-4.c: New HImode test case. + +2023-04-29 Jeff Law <jlaw@ventanamicro> + + * gcc.target/mips/mips-ps-type-2.c: Adjust branch cost to + encourage if-conversion. Skip for -Os. + * gcc.target/mips/movcc-3.c: Similarly. + +2023-04-29 Fei Gao <gaofei@eswincomputing.com> + + * gcc.target/riscv/rv32e_stack.c: New test. + 2023-04-28 Hans-Peter Nilsson <hp@axis.com> * lib/scanasm.exp (parse_function_bodies): Set fluff to include -- GitLab