From 91f59d8bf44e24f67a9194dfdfdbad4b7279b772 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod <amacleod@redhat.com>
Date: Tue, 29 Nov 2011 19:42:44 +0000
Subject: [PATCH] re PR target/50123 (cmpxchg generated for atomic and with
zero/or with -1)
2011-11-29 Andrew MacLeod <amacleod@redhat.com>
PR target/50123
* optabs.c (maybe_optimize_fetch_op): New. Look for more optimal
instructions for a FECTH_OP or OP_FECTH sequence.
(expand_atomic_fetch_op): Call maybe_optimize_fetch_op.
* testsuite/gcc.dg/atomic-op-optimize.c: New. Test for optimizations.
From-SVN: r181815
---
gcc/ChangeLog | 7 ++++
gcc/optabs.c | 40 +++++++++++++++++++++++
gcc/testsuite/ChangeLog | 5 +++
gcc/testsuite/gcc.dg/atomic-op-optimize.c | 20 ++++++++++++
4 files changed, 72 insertions(+)
create mode 100644 gcc/testsuite/gcc.dg/atomic-op-optimize.c
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cc71361206ed..921b4f930498 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2011-11-29 Andrew MacLeod <amacleod@redhat.com>
+
+ PR target/50123
+ * optabs.c (maybe_optimize_fetch_op): New. Look for more optimal
+ instructions for a FECTH_OP or OP_FECTH sequence.
+ (expand_atomic_fetch_op): Call maybe_optimize_fetch_op.
+
2011-11-29 Uros Bizjak <ubizjak@gmail.com>
* config/i386/sync.md (UNSPEC_LDA, UNSPEC_STA): New unspecs.
diff --git a/gcc/optabs.c b/gcc/optabs.c
index a1917cc32204..c3f81dfe2d22 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -7943,6 +7943,41 @@ get_atomic_op_for_code (struct atomic_op_functions *op, enum rtx_code code)
}
}
+/* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
+ using memory order MODEL. If AFTER is true the operation needs to return
+ the value of *MEM after the operation, otherwise the previous value.
+ TARGET is an optional place to place the result. The result is unused if
+ it is const0_rtx.
+ Return the result if there is a better sequence, otherwise NULL_RTX. */
+
+static rtx
+maybe_optimize_fetch_op (rtx target, rtx mem, rtx val, enum rtx_code code,
+ enum memmodel model, bool after)
+{
+ /* If the value is prefetched, or not used, it may be possible to replace
+ the sequence with a native exchange operation. */
+ if (!after || target == const0_rtx)
+ {
+ /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
+ if (code == AND && val == const0_rtx)
+ {
+ if (target == const0_rtx)
+ target = gen_reg_rtx (GET_MODE (mem));
+ return maybe_emit_atomic_exchange (target, mem, val, model);
+ }
+
+ /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
+ if (code == IOR && val == constm1_rtx)
+ {
+ if (target == const0_rtx)
+ target = gen_reg_rtx (GET_MODE (mem));
+ return maybe_emit_atomic_exchange (target, mem, val, model);
+ }
+ }
+
+ return NULL_RTX;
+}
+
/* Try to emit an instruction for a specific operation varaition.
OPTAB contains the OP functions.
TARGET is an optional place to return the result. const0_rtx means unused.
@@ -8028,6 +8063,11 @@ expand_atomic_fetch_op (rtx target, rtx mem, rtx val, enum rtx_code code,
get_atomic_op_for_code (&optab, code);
+ /* Check to see if there are any better instructions. */
+ result = maybe_optimize_fetch_op (target, mem, val, code, model, after);
+ if (result)
+ return result;
+
/* Check for the case where the result isn't used and try those patterns. */
if (unused_result)
{
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c8d90be340de..a5a39e3c4d13 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2011-11-29 Andrew MacLeod <amacleod@redhat.com>
+
+ PR target/50123
+ * gcc.dg/atomic-op-optimize.c: New. Test for optimizations.
+
2011-11-29 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/ppc-target-4.c: New file to test target
diff --git a/gcc/testsuite/gcc.dg/atomic-op-optimize.c b/gcc/testsuite/gcc.dg/atomic-op-optimize.c
new file mode 100644
index 000000000000..d2e960a0ceee
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/atomic-op-optimize.c
@@ -0,0 +1,20 @@
+/* Both these atomic operations should be optimized to an exchange operation.
+ Test that it at happens on x86 by making sure there are 2 xchg's and no
+ compare_exchange loop. */
+
+/* { dg-require-effective-target sync_int_long } */
+/* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-final { scan-assembler-times "cmpxchg" 0 } } */
+/* { dg-final { scan-assembler-times "xchg" 2 } } */
+
+int x;
+
+int f()
+{
+ return __atomic_fetch_and (&x, 0, __ATOMIC_RELAXED);
+}
+
+int g()
+{
+ return __atomic_fetch_or (&x, -1, __ATOMIC_RELAXED);
+}
--
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