diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b673b42fc74414591a1a1dc48a58d9d9cb0bdb2a..f2474ac30432923f1685f22b2bac864029e10e3e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,7 @@
 2003-06-17  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 
+	* config/mips/mips.md (trap): Use break 0 when !TARGET_GAS.
+
 	* config/mips/iris6-o32.h (MIPS_ISA_DEFAULT): Remove.
 	(MIPS_CPU_STRING_DEFAULT): Redefine to mips2.
 
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index b26960a9a0f7b7a57bfca66d419a689133d365d8..2841369f92f2ce0694400c4ce0d61055da6aeb47 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -640,7 +640,8 @@
 {
   if (ISA_HAS_COND_TRAP)
     return \"teq\\t$0,$0\";
-  else if (TARGET_MIPS16)
+  /* The IRIX 6 O32 assembler requires the first break operand.  */
+  else if (TARGET_MIPS16 || ! TARGET_GAS)
     return \"break 0\";
   else
     return \"break\";