diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 57e8d9c8e6798b7e4e73981d82e206574e5a9ab2..30441e674d024a479adbe346494cacdd5f8f44e5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,20 @@
+2009-01-14 Daniel Jacobowitz <dan@codesourcery.com>
+ Nathan Froyd <froydnj@codesourcery.com>
+ Joseph Myers <joseph@codesourcery.com>
+
+ * lib/target-supports.exp (check_effective_target_powerpc_spe_nocache):
+ New function.
+ * gcc.target/powerpc/20030218-1.c: Skip if not powerpc_spe_nocache
+ and use consistent CFLAGS.
+ * gcc.target/powerpc/20030505.c: Likewise.
+ * gcc.target/powerpc/20081204-1.c: Likewise.
+ * gcc.target/powerpc/ppc-spe.c: Likewise.
+ * gcc.target/powerpc/spe1.c: Likewise.
+ * g++.dg/ext/spe1.C: Likewise.
+ * g++.dg/other/opaque-1.C: Likewise.
+ * g++.dg/other/opaque-2.C: Likewise.
+ * g++.dg/other/opaque-3.C: Likewise.
+
2009-01-14 Mark Mitchell <mark@codesourcery.com>
* gcc.dg/vect/vect-105.c: Prevent compiler from hoisting abort
diff --git a/gcc/testsuite/g++.dg/ext/spe1.C b/gcc/testsuite/g++.dg/ext/spe1.C
index fdd213964b4f0643816610a146c450cc27ba70c5..8b1e630ecc03734cf0fc27f2de71db04bd25d5c2 100644
--- a/gcc/testsuite/g++.dg/ext/spe1.C
+++ b/gcc/testsuite/g++.dg/ext/spe1.C
@@ -1,5 +1,6 @@
-/* { dg-do compile { target powerpc-*-eabi* } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
typedef int v2si __attribute__ ((vector_size (8)));
diff --git a/gcc/testsuite/g++.dg/other/opaque-1.C b/gcc/testsuite/g++.dg/other/opaque-1.C
index fa79f6f2a1e4cc012a3ec1cc61400f86e58386b1..5cdaeafe31aa8203108a24c93881b472e4f48900 100644
--- a/gcc/testsuite/g++.dg/other/opaque-1.C
+++ b/gcc/testsuite/g++.dg/other/opaque-1.C
@@ -1,4 +1,6 @@
-/* { dg-do run { target { powerpc*-*-* && powerpc_spe } } } */
+/* { dg-do run } */
+/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
#define __vector __attribute__((vector_size(8)))
typedef float __vector __ev64_fs__;
diff --git a/gcc/testsuite/g++.dg/other/opaque-2.C b/gcc/testsuite/g++.dg/other/opaque-2.C
index 6b13ba2810db83aa0b29c7afdd17cbb454dba7e8..3bb4af2c7786acfed33607aeea2425bec88a09f9 100644
--- a/gcc/testsuite/g++.dg/other/opaque-2.C
+++ b/gcc/testsuite/g++.dg/other/opaque-2.C
@@ -1,5 +1,6 @@
-/* { dg-do compile { target powerpc-*-eabi* powerpc*-*-linux*spe* } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
#define __vector __attribute__((vector_size(8)))
typedef float __vector __ev64_fs__;
diff --git a/gcc/testsuite/g++.dg/other/opaque-3.C b/gcc/testsuite/g++.dg/other/opaque-3.C
index cf8119ffcac87b6342ccc60a939bc8e982b25455..5ece652c0cd1cb54c6e92006249d316f2568f26f 100644
--- a/gcc/testsuite/g++.dg/other/opaque-3.C
+++ b/gcc/testsuite/g++.dg/other/opaque-3.C
@@ -1,5 +1,6 @@
-/* { dg-do compile { target powerpc-*-eabi* powerpc*-*-linux*spe* } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
__ev64_opaque__ o;
#define v __attribute__((vector_size(8)))
diff --git a/gcc/testsuite/gcc.target/powerpc/20030218-1.c b/gcc/testsuite/gcc.target/powerpc/20030218-1.c
index 024f637f8ec062edcd0891a118e2f6516505608b..2a1c4e6d253b1c5f2f2f7f2e192ea9c7b2ac98dc 100644
--- a/gcc/testsuite/gcc.target/powerpc/20030218-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/20030218-1.c
@@ -1,5 +1,6 @@
-/* { dg-do compile { target powerpc-*-eabi* } } */
-/* { dg-options "-mspe=yes -mfloat-gprs=single" } */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
/* Test vectors that can interconvert without a cast. */
@@ -19,7 +20,7 @@ main (void)
/* Just because this is a V2SI, it doesn't make it an opaque. */
vint = vshort; /* { dg-message "note: use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts" } */
- /* { dg-error "incompatible types when assigning" "" { target *-*-* } 21 } */
+ /* { dg-error "incompatible types when assigning" "" { target *-*-* } 22 } */
return 0;
}
diff --git a/gcc/testsuite/gcc.target/powerpc/20030505.c b/gcc/testsuite/gcc.target/powerpc/20030505.c
index a8283934d71f7af720212baa5aa365253371f644..2bef590bf7b599caf927dafdccf6a722293a46c4 100644
--- a/gcc/testsuite/gcc.target/powerpc/20030505.c
+++ b/gcc/testsuite/gcc.target/powerpc/20030505.c
@@ -1,5 +1,6 @@
-/* { dg-do compile { target powerpc-*-eabi* } } */
+/* { dg-do compile } */
/* { dg-options "-W -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
#define __vector __attribute__((vector_size(8)))
diff --git a/gcc/testsuite/gcc.target/powerpc/20081204-1.c b/gcc/testsuite/gcc.target/powerpc/20081204-1.c
index ba4df8f3e29928cb02b6880060f952bffd181720..8a973d0ec52e8bdde38ed63de5219bc32599a793 100644
--- a/gcc/testsuite/gcc.target/powerpc/20081204-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/20081204-1.c
@@ -2,6 +2,8 @@
TARGET_HARD_FLOAT && !TARGET_FPRS. */
/* { dg-do compile } */
/* { dg-options "-mcpu=750 -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
static int comp(const void *a,const void *b){
return (*(float *)a<*(float *)b)-(*(float *)a>*(float *)b);
}
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-spe.c b/gcc/testsuite/gcc.target/powerpc/ppc-spe.c
index 841073b22b78fe241437649e13d1582281380b7d..b56439433407c10a86b6f1d473603fa0de67694c 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-spe.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-spe.c
@@ -1,5 +1,6 @@
-/* { dg-do compile { target powerpc-*-eabi* } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
/* (Test with -O0 so we don't optimize any of them away). */
diff --git a/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c b/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c
index d12f6696eb05d2613530bf1b053f294746b07626..09f8134829c87ceff6312eb21e1ab20af60fe81a 100644
--- a/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c
+++ b/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c
@@ -1,6 +1,6 @@
-/* { dg-do compile { target powerpc*-*-* } } */
-/* { dg-require-effective-target powerpc_spe } */
-/* { dg-options "-O -mspe=yes" } */
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
/* { dg-final { scan-assembler "evstdd" } } */
void foo(void)
diff --git a/gcc/testsuite/gcc.target/powerpc/spe1.c b/gcc/testsuite/gcc.target/powerpc/spe1.c
index 9803d8fdb7f1dbbf58f160c443c6be1f8aaff9bb..ddbb5a6e1c95e012a508c96e99b09f7aa030dac7 100644
--- a/gcc/testsuite/gcc.target/powerpc/spe1.c
+++ b/gcc/testsuite/gcc.target/powerpc/spe1.c
@@ -1,5 +1,6 @@
-/* { dg-do compile { target powerpc-*-eabi* } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
/* (Test with -O0 so we don't optimize any of them away). */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index af806be6dd181dd4a35b798b3b45002f9c87e075..aaefa60cbcb37151fcd29954e520238024f7df2b 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1535,6 +1535,23 @@ proc check_effective_target_powerpc_spu { } {
}
}
+# Return 1 if this is a PowerPC SPE target. The check includes options
+# specified by dg-options for this test, so don't cache the result.
+
+proc check_effective_target_powerpc_spe_nocache { } {
+ if { [istarget powerpc*-*-*] } {
+ return [check_no_compiler_messages_nocache powerpc_spe object {
+ #ifndef __SPE__
+ #error not SPE
+ #else
+ int dummy;
+ #endif
+ } [current_compiler_flags]]
+ } else {
+ return 0
+ }
+}
+
# Return 1 if this is a PowerPC target with SPE enabled.
proc check_effective_target_powerpc_spe { } {