From 9eb8c09fdae1c41a03d30a1a386dafbf25cb1b82 Mon Sep 17 00:00:00 2001
From: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Thu, 5 Dec 2013 07:54:43 +0000
Subject: [PATCH] ia64.md (prologue_allocate_stack): Block auto- generation of
predicated version.
ChangeLog/
* config/ia64/ia64.md (prologue_allocate_stack): Block auto-
generation of predicated version.
(epilogue_deallocate_stack): Ditto.
(prologue_allocate_stack_pr): Add explicit predicated version.
(epilogue_deallocate_stack_pr): Ditto.
* config/ia64/ia64.c (ia64_single_set): Use explicit versions.
testsuite/ChangeLog/
* gcc.target/ia64/pr52731.c: New.
From-SVN: r205692
---
gcc/ChangeLog | 9 ++++++
gcc/config/ia64/ia64.c | 2 ++
gcc/config/ia64/ia64.md | 41 +++++++++++++++++++++++--
gcc/testsuite/ChangeLog | 4 +++
gcc/testsuite/gcc.target/ia64/pr52731.c | 19 ++++++++++++
5 files changed, 73 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/ia64/pr52731.c
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e5ed55cee1c0..ffbd2948fde8 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2013-12-05 Kirill Yukhin <kirill.yukhin@intel.com>
+
+ * config/ia64/ia64.md (prologue_allocate_stack): Block auto-
+ generation of predicated version.
+ (epilogue_deallocate_stack): Ditto.
+ (prologue_allocate_stack_pr): Add explicit predicated version.
+ (epilogue_deallocate_stack_pr): Ditto.
+ * config/ia64/ia64.c (ia64_single_set): Use explicit version.
+
2013-12-05 Alan Modra <amodra@gmail.com>
* configure.ac (BUILD_CXXFLAGS) Don't use ALL_CXXFLAGS for
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index df4a4b02d4cb..8f305c1153cb 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -7159,7 +7159,9 @@ ia64_single_set (rtx insn)
switch (recog_memoized (insn))
{
case CODE_FOR_prologue_allocate_stack:
+ case CODE_FOR_prologue_allocate_stack_pr:
case CODE_FOR_epilogue_deallocate_stack:
+ case CODE_FOR_epilogue_deallocate_stack_pr:
ret = XVECEXP (x, 0, 0);
break;
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 4d9d4e0129f5..bc4e8cbfd1b2 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -4652,6 +4652,8 @@
;; This prevents the scheduler from moving the SP decrement past FP-relative
;; stack accesses. This is the same as adddi3 plus the extra set.
+;; Explicit predicated version of insn needed to check by CODE_FOR_
+;; in ia64_single_set, where despite of 2 sets this define_insn should be OK.
(define_insn "prologue_allocate_stack"
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
@@ -4664,10 +4666,31 @@
add %0 = %1, %2
adds %0 = %2, %1
addl %0 = %2, %1"
- [(set_attr "itanium_class" "ialu")])
+ [(set_attr "itanium_class" "ialu")
+ (set_attr "predicable" "no")])
+
+(define_insn "prologue_allocate_stack_pr"
+ [(cond_exec (match_operator 0 ("predicate_operator")
+ [(match_operand:BI 1 ("register_operand") ("c,c,c"))
+ (const_int 0)])
+ (parallel
+ [(set (match_operand:DI 2 "register_operand" "=r,r,r")
+ (plus:DI (match_operand:DI 3 "register_operand" "%r,r,a")
+ (match_operand:DI 4 "gr_reg_or_22bit_operand" "r,I,J")))
+ (set (match_operand:DI 5 "register_operand" "+r,r,r")
+ (match_dup 5))]))]
+ ""
+ "@
+ (%J0) add %2 = %3, %4
+ (%J0) adds %2 = %3, %4
+ (%J0) addl %2 = %3, %4"
+ [(set_attr "itanium_class" "ialu")
+ (set_attr "predicable" "no")])
;; This prevents the scheduler from moving the SP restore past FP-relative
;; stack accesses. This is similar to movdi plus the extra set.
+;; Explicit predicated version of insn needed to check by CODE_FOR_
+;; in ia64_single_set, where despite of 2 sets this define_insn should be OK.
(define_insn "epilogue_deallocate_stack"
[(set (match_operand:DI 0 "register_operand" "=r")
@@ -4675,7 +4698,21 @@
(set (match_dup 1) (match_dup 1))]
""
"mov %0 = %1"
- [(set_attr "itanium_class" "ialu")])
+ [(set_attr "itanium_class" "ialu")
+ (set_attr "predicable" "no")])
+
+(define_insn "epilogue_deallocate_stack_pr"
+ [(cond_exec (match_operator 0 ("predicate_operator")
+ [(match_operand:BI 1 ("register_operand") ("c"))
+ (const_int 0)])
+ (parallel
+ [(set (match_operand:DI 2 "register_operand" "=r")
+ (match_operand:DI 3 "register_operand" "+r"))
+ (set (match_dup 3) (match_dup 3))]))]
+ ""
+ "(%J0) mov %2 = %3"
+ [(set_attr "itanium_class" "ialu")
+ (set_attr "predicable" "no")])
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for EH handling
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8b8426526ac2..07d071f6abc8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2013-12-05 Kirill Yukhin <kirill.yukhin@intel.com>
+
+ * gcc.target/ia64/pr52731.c: New.
+
2013-12-04 Jeff Law <law@redhat.com>
* gcc.dg/pr38984.c: Use -fno-isolate-erroneous-paths-dereference.
diff --git a/gcc/testsuite/gcc.target/ia64/pr52731.c b/gcc/testsuite/gcc.target/ia64/pr52731.c
new file mode 100644
index 000000000000..50ef1d78d757
--- /dev/null
+++ b/gcc/testsuite/gcc.target/ia64/pr52731.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target ia64-*-* } } */
+/* { dg-options "-O2" } */
+
+char* area;
+long int area_size;
+char* base;
+
+void fun(unsigned long int addr)
+{
+ unsigned long int size32 = (addr + 4096 - 1) & ~(4096 - 1);
+ unsigned long int size = size32 * sizeof(unsigned int);
+
+ if (size > 0) {
+ size = (size + 1) & ~(1);
+ }
+
+ area_size = size;
+ area = base + size;
+}
--
GitLab