diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c
new file mode 100644
index 0000000000000000000000000000000000000000..8cf0d06efdb2e2c01d24ec6165f10313ac2ae908
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c
new file mode 100644
index 0000000000000000000000000000000000000000..a26d3943e27bd4911ac5607e82afdb79ce5e25b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c
new file mode 100644
index 0000000000000000000000000000000000000000..4ef1351dd2999c98a59c68d245077099c6c91452
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c
new file mode 100644
index 0000000000000000000000000000000000000000..4879103c1358d2bf434af66e3bdb743937af744f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-5.c
new file mode 100644
index 0000000000000000000000000000000000000000..c9605cc928a3edb67bb47fe230e89417e2a73128
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-5.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T  int8_t
+#define T1 int8_t
+#define T2 uint8_t
+
+DEF_VEC_SAT_S_ADD_FMT_2_WRAP (T1, T2, INT8_MIN, INT8_MAX)
+
+#define test_data          TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+  RUN_VEC_SAT_S_ADD_FMT_2_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-6.c
new file mode 100644
index 0000000000000000000000000000000000000000..07dcc58dfda32eaad7b31a86a8ff25f019d2a8ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-6.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T  int16_t
+#define T1 int16_t
+#define T2 uint16_t
+
+DEF_VEC_SAT_S_ADD_FMT_2_WRAP (T1, T2, INT16_MIN, INT16_MAX)
+
+#define test_data          TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+  RUN_VEC_SAT_S_ADD_FMT_2_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-7.c
new file mode 100644
index 0000000000000000000000000000000000000000..696d1fcfc53f82c3112904ce638b236ca360c3d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-7.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T  int32_t
+#define T1 int32_t
+#define T2 uint32_t
+
+DEF_VEC_SAT_S_ADD_FMT_2_WRAP (T1, T2, INT32_MIN, INT32_MAX)
+
+#define test_data          TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+  RUN_VEC_SAT_S_ADD_FMT_2_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-8.c
new file mode 100644
index 0000000000000000000000000000000000000000..5106c23a26f8379046a93ef245d24d92eeb068fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-8.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T  int64_t
+#define T1 int64_t
+#define T2 uint64_t
+
+DEF_VEC_SAT_S_ADD_FMT_2_WRAP (T1, T2, INT64_MIN, INT64_MAX)
+
+#define test_data          TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+  RUN_VEC_SAT_S_ADD_FMT_2_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
index 9a16804d806ee5cfa4a2bf4f0f6b60dd6d28bb51..1bac47e67a58af6a26c841b48d2abff1e0814771 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
@@ -241,11 +241,35 @@ vec_sat_s_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
 #define DEF_VEC_SAT_S_ADD_FMT_1_WRAP(T, UT, MIN, MAX) \
   DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX)
 
+#define DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX)                     \
+void __attribute__((noinline))                                       \
+vec_sat_s_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
+{                                                                    \
+  unsigned i;                                                        \
+  for (i = 0; i < limit; i++)                                        \
+    {                                                                \
+      T x = op_1[i];                                                 \
+      T y = op_2[i];                                                 \
+      T sum = (UT)x + (UT)y;                                         \
+      if ((x ^ y) < 0 || (sum ^ x) >= 0)                             \
+        out[i] = sum;                                                \
+      else                                                           \
+        out[i] = x < 0 ? MIN : MAX;                                  \
+    }                                                                \
+}
+#define DEF_VEC_SAT_S_ADD_FMT_2_WRAP(T, UT, MIN, MAX) \
+  DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX)
+
 #define RUN_VEC_SAT_S_ADD_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_s_add_##T##_fmt_1(out, op_1, op_2, N)
 #define RUN_VEC_SAT_S_ADD_FMT_1_WRAP(T, out, op_1, op_2, N) \
   RUN_VEC_SAT_S_ADD_FMT_1(T, out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_S_ADD_FMT_2(T, out, op_1, op_2, N) \
+  vec_sat_s_add_##T##_fmt_2(out, op_1, op_2, N)
+#define RUN_VEC_SAT_S_ADD_FMT_2_WRAP(T, out, op_1, op_2, N) \
+  RUN_VEC_SAT_S_ADD_FMT_2(T, out, op_1, op_2, N)
+
 /******************************************************************************/
 /* Saturation Sub (Unsigned and Signed)                                       */
 /******************************************************************************/