From a67ed43f1f1e0a64e55a207c7e8626330a91559d Mon Sep 17 00:00:00 2001
From: Aldy Hernandez <aldyh@redhat.com>
Date: Mon, 23 Dec 2002 22:08:57 +0000
Subject: [PATCH] altivec.md (mulv4sf3): Rewrite to add -0.0 vector.
2002-12-23 Aldy Hernandez <aldyh@redhat.com>
PR/8763
* config/rs6000/altivec.md (mulv4sf3): Rewrite to add -0.0 vector.
(altivec_vspltisw_v4sf): Name pattern.
(altivec_vslw_v4sf): New pattern.
From-SVN: r60453
---
gcc/ChangeLog | 7 +++++++
gcc/config/rs6000/altivec.md | 35 ++++++++++++++++++++++++++---------
2 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 37b47fd54a17..6fd530633cd4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2002-12-23 Aldy Hernandez <aldyh@redhat.com>
+
+ PR/8763
+ * config/rs6000/altivec.md (mulv4sf3): Rewrite to add -0.0 vector.
+ (altivec_vspltisw_v4sf): Name pattern.
+ (altivec_vslw_v4sf): New pattern.
+
2002-12-23 Joseph S. Myers <jsm@polyomino.org.uk>
* doc/include/gcc-common.texi: Define DEVELOPMENT.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 063fe522135f..c3f67d2210ee 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -490,18 +490,27 @@
"vmaddfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
-;; The unspec here is a vec splat of 0. We do multiply as a fused
-;; multiply-add with an add of a 0 vector.
+;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
(define_expand "mulv4sf3"
- [(set (match_dup 3) (unspec:V4SF [(const_int 0)] 142))
- (set (match_operand:V4SF 0 "register_operand" "=v")
- (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
- (match_operand:V4SF 2 "register_operand" "v"))
- (match_dup 3)))]
+ [(use (match_operand:V4SF 0 "register_operand" ""))
+ (use (match_operand:V4SF 1 "register_operand" ""))
+ (use (match_operand:V4SF 2 "register_operand" ""))]
"TARGET_ALTIVEC && TARGET_FUSED_MADD"
"
-{ operands[3] = gen_reg_rtx (V4SFmode); }")
+{
+ rtx neg0;
+
+ /* Generate [-0.0, -0.0, -0.0, -0.0]. */
+ neg0 = gen_reg_rtx (V4SFmode);
+ emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1)));
+ emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
+
+ /* Use the multiply-add. */
+ emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
+ neg0));
+ DONE;
+}")
;; Fused multiply subtract
(define_insn "altivec_vnmsubfp"
@@ -1043,6 +1052,14 @@
"vslw %0,%1,%2"
[(set_attr "type" "vecsimple")])
+(define_insn "altivec_vslw_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=v")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
+ (match_operand:V4SF 2 "register_operand" "v")] 109))]
+ "TARGET_ALTIVEC"
+ "vslw %0,%1,%2"
+ [(set_attr "type" "vecsimple")])
+
(define_insn "altivec_vsl"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
@@ -1315,7 +1332,7 @@
"vspltisw %0, %1"
[(set_attr "type" "vecperm")])
-(define_insn ""
+(define_insn "altivec_vspltisw_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
"TARGET_ALTIVEC"
--
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