From aad0c3e197f21fac169917e187c61764a8a3ff3d Mon Sep 17 00:00:00 2001
From: Pan Li <pan2.li@intel.com>
Date: Mon, 18 Sep 2023 11:19:33 +0800
Subject: [PATCH] RISC-V: Support VLS mode for vec_set
This patch would like to add the VLS support vec_set, both INT
and FP are included.
Give sample code as below:
typedef long long vl_t \
__attribute__((vector_size(2 * sizeof (long long))));
vl_t init_vl (vl_t v, unsigned index, unsigned value)
{
v[index] = value;
return v;
}
Before this patch:
init_vl:
addi sp,sp,-16
vsetivli zero,2,e64,m1,ta,ma
vle64.v v1,0(a1)
vse64.v v1,0(sp)
slli a4,a2,32
srli a2,a4,29
add a2,sp,a2
slli a3,a3,32
srli a3,a3,32
sd a3,0(a2)
vle64.v v1,0(sp)
vse64.v v1,0(a0)
addi sp,sp,16
jr ra
After this patch:
init_vl:
vsetivli zero,2,e64,m1,ta,ma
vle64.v v1,0(a1)
slli a3,a3,32
srli a3,a3,32
addi a5,a2,1
vsetvli zero,a5,e64,m1,tu,ma
vmv.v.x v2,a3
vslideup.vx v1,v2,a2
vsetivli zero,2,e64,m1,ta,ma
vse64.v v1,0(a0)
ret
Please note this patch depends the RVV SCALAR_MOVE_MERGED_OP bugfix.
gcc/ChangeLog:
* config/riscv/autovec.md: Extend to vls mode.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: New macros.
* gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/autovec.md | 4 +--
.../gcc.target/riscv/rvv/autovec/vls/def.h | 18 ++++++++++
.../riscv/rvv/autovec/vls/vec-set-1.c | 35 +++++++++++++++++++
.../riscv/rvv/autovec/vls/vec-set-10.c | 31 ++++++++++++++++
.../riscv/rvv/autovec/vls/vec-set-11.c | 29 +++++++++++++++
.../riscv/rvv/autovec/vls/vec-set-12.c | 21 +++++++++++
.../riscv/rvv/autovec/vls/vec-set-13.c | 20 +++++++++++
.../riscv/rvv/autovec/vls/vec-set-14.c | 19 ++++++++++
.../riscv/rvv/autovec/vls/vec-set-15.c | 18 ++++++++++
.../riscv/rvv/autovec/vls/vec-set-16.c | 21 +++++++++++
.../riscv/rvv/autovec/vls/vec-set-17.c | 20 +++++++++++
.../riscv/rvv/autovec/vls/vec-set-18.c | 19 ++++++++++
.../riscv/rvv/autovec/vls/vec-set-19.c | 18 ++++++++++
.../riscv/rvv/autovec/vls/vec-set-2.c | 33 +++++++++++++++++
.../riscv/rvv/autovec/vls/vec-set-20.c | 20 +++++++++++
.../riscv/rvv/autovec/vls/vec-set-21.c | 19 ++++++++++
.../riscv/rvv/autovec/vls/vec-set-22.c | 18 ++++++++++
.../riscv/rvv/autovec/vls/vec-set-3.c | 31 ++++++++++++++++
.../riscv/rvv/autovec/vls/vec-set-4.c | 29 +++++++++++++++
.../riscv/rvv/autovec/vls/vec-set-5.c | 35 +++++++++++++++++++
.../riscv/rvv/autovec/vls/vec-set-6.c | 33 +++++++++++++++++
.../riscv/rvv/autovec/vls/vec-set-7.c | 31 ++++++++++++++++
.../riscv/rvv/autovec/vls/vec-set-8.c | 29 +++++++++++++++
.../riscv/rvv/autovec/vls/vec-set-9.c | 33 +++++++++++++++++
24 files changed, 582 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index f6d8616d5a20..b968c6ddef3f 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1393,9 +1393,9 @@
;; -------------------------------------------------------------------------
(define_expand "vec_set<mode>"
- [(match_operand:V 0 "register_operand")
+ [(match_operand:V_VLS 0 "register_operand")
(match_operand:<VEL> 1 "register_operand")
- (match_operand 2 "nonmemory_operand")]
+ (match_operand 2 "nonmemory_operand")]
"TARGET_VECTOR"
{
/* If we set the first element, emit an v(f)mv.s.[xf]. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 59f31d03be10..4d32de5a61f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -439,3 +439,21 @@ typedef double v512df __attribute__ ((vector_size (4096)));
TYPE1 v = {__VA_ARGS__}; \
*(TYPE1 *) out = v; \
}
+
+#define DEF_VEC_SET_IMM_INDEX(PREFIX, VECTOR, TYPE, INDEX) \
+ VECTOR __attribute__ ((noinline, noclone)) \
+ PREFIX##_##VECTOR##_##INDEX (VECTOR v, TYPE a) \
+ { \
+ v[INDEX] = a; \
+ \
+ return v; \
+ }
+
+#define DEF_VEC_SET_SCALAR_INDEX(PREFIX, VECTOR, TYPE) \
+ VECTOR __attribute__ ((noinline, noclone)) \
+ PREFIX##_##VECTOR##_##TYPE (VECTOR v, TYPE a, unsigned index) \
+ { \
+ v[index] = a; \
+ \
+ return v; \
+ }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
new file mode 100644
index 000000000000..d53fdc221628
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2048qi, int8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4096qi, int8_t, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2048qi, int8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4096qi, int8_t, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 12 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
new file mode 100644
index 000000000000..c9242362372c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1sf, float, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2sf, float, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4sf, float, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8sf, float, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16sf, float, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32sf, float, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64sf, float, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128sf, float, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256sf, float, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512sf, float, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024sf, float, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2sf, float, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4sf, float, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8sf, float, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16sf, float, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32sf, float, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64sf, float, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128sf, float, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256sf, float, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512sf, float, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024sf, float, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vfmv\.s\.f\s+v[0-9]+,\s*[fa]+[0-9]+} 10 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
new file mode 100644
index 000000000000..4ec86789d80a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1df, double, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2df, double, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4df, double, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8df, double, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16df, double, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32df, double, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64df, double, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128df, double, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256df, double, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512df, double, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2df, double, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4df, double, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8df, double, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16df, double, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32df, double, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64df, double, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128df, double, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256df, double, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512df, double, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vfmv\.s\.f\s+v[0-9]+,\s*[fa]+[0-9]+} 9 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 9 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
new file mode 100644
index 000000000000..4436830307b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048qi, int8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4096qi, int8_t)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[axt][0-9]+} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
new file mode 100644
index 000000000000..037a4a6f71a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024hi, int16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048hi, int16_t)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[axt][0-9]+} 11 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
new file mode 100644
index 000000000000..4dd58884d79b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1si, int32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2si, int32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4si, int32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8si, int32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16si, int32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32si, int32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64si, int32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128si, int32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256si, int32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512si, int32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024si, int32_t)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
new file mode 100644
index 000000000000..77eeed49a992
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1di, int64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2di, int64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4di, int64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8di, int64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16di, int64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32di, int64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64di, int64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128di, int64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256di, int64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512di, int64_t)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 9 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
new file mode 100644
index 000000000000..4f2bb2c75084
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048uqi, uint8_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4096uqi, uint8_t)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
new file mode 100644
index 000000000000..9376aee2ac22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024uhi, uint16_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048uhi, uint16_t)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 11 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c
new file mode 100644
index 000000000000..ade887ea3bef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1usi, uint32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2usi, uint32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4usi, uint32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8usi, uint32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16usi, uint32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32usi, uint32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64usi, uint32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128usi, uint32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256usi, uint32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512usi, uint32_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024usi, uint32_t)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c
new file mode 100644
index 000000000000..7106bd936ad0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1udi, uint64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2udi, uint64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4udi, uint64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8udi, uint64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16udi, uint64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32udi, uint64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64udi, uint64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128udi, uint64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256udi, uint64_t)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512udi, uint64_t)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 9 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c
new file mode 100644
index 000000000000..6132bb4945a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024hi, int16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2048hi, int16_t, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2hi, int16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4hi, int16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8hi, int16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16hi, int16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32hi, int16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64hi, int16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128hi, int16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256hi, int16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512hi, int16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024hi, int16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2048hi, int16_t, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 11 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 11 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c
new file mode 100644
index 000000000000..2da3e3c18a4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024hf, _Float16)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048hf, _Float16)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 11 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c
new file mode 100644
index 000000000000..db2682ad3fd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1sf, float)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2sf, float)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4sf, float)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8sf, float)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16sf, float)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32sf, float)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64sf, float)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128sf, float)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256sf, float)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512sf, float)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024sf, float)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c
new file mode 100644
index 000000000000..3bb3936c006f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v1df, double)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v2df, double)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v4df, double)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v8df, double)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v16df, double)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v32df, double)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v64df, double)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v128df, double)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v256df, double)
+DEF_VEC_SET_SCALAR_INDEX (vec_set, v512df, double)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[axt][0-9]+} 9 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c
new file mode 100644
index 000000000000..6080060b60df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1si, int32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2si, int32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4si, int32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8si, int32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16si, int32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32si, int32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64si, int32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128si, int32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256si, int32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512si, int32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024si, int32_t, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2si, int32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4si, int32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8si, int32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16si, int32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32si, int32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64si, int32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128si, int32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256si, int32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512si, int32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024si, int32_t, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 10 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c
new file mode 100644
index 000000000000..09852f7ca1d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1di, int64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2di, int64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4di, int64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8di, int64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16di, int64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32di, int64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64di, int64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128di, int64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256di, int64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512di, int64_t, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2di, int64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4di, int64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8di, int64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16di, int64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32di, int64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64di, int64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128di, int64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256di, int64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512di, int64_t, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 9 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 9 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c
new file mode 100644
index 000000000000..b6a4d1a2c8bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2048uqi, uint8_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4096uqi, uint8_t, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2048uqi, uint8_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4096uqi, uint8_t, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 12 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c
new file mode 100644
index 000000000000..11e22db53f49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024uhi, uint16_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2048uhi, uint16_t, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2uhi, uint16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4uhi, uint16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8uhi, uint16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16uhi, uint16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32uhi, uint16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64uhi, uint16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128uhi, uint16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256uhi, uint16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512uhi, uint16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024uhi, uint16_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2048uhi, uint16_t, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 11 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 11 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c
new file mode 100644
index 000000000000..d4ce093f2016
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1usi, uint32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2usi, uint32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4usi, uint32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8usi, uint32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16usi, uint32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32usi, uint32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64usi, uint32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128usi, uint32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256usi, uint32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512usi, uint32_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024usi, uint32_t, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2usi, uint32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4usi, uint32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8usi, uint32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16usi, uint32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32usi, uint32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64usi, uint32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128usi, uint32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256usi, uint32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512usi, uint32_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024usi, uint32_t, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 10 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c
new file mode 100644
index 000000000000..4beb2b0b9be4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1udi, uint64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2udi, uint64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4udi, uint64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8udi, uint64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16udi, uint64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32udi, uint64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64udi, uint64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128udi, uint64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256udi, uint64_t, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512udi, uint64_t, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2udi, uint64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4udi, uint64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8udi, uint64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16udi, uint64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32udi, uint64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64udi, uint64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128udi, uint64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256udi, uint64_t, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512udi, uint64_t, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+} 9 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 9 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c
new file mode 100644
index 000000000000..b59f3f3d1215
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v1hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024hf, _Float16, 0)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2048hf, _Float16, 0)
+
+DEF_VEC_SET_IMM_INDEX (vec_set, v2hf, _Float16, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v4hf, _Float16, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v8hf, _Float16, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v16hf, _Float16, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v32hf, _Float16, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v64hf, _Float16, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v128hf, _Float16, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v256hf, _Float16, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v512hf, _Float16, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v1024hf, _Float16, 1)
+DEF_VEC_SET_IMM_INDEX (vec_set, v2048hf, _Float16, 1)
+
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vfmv\.s\.f\s+v[0-9]+,\s*[fa]+[0-9]+} 11 } } */
+/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,\s*1} 11 } } */
--
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