From b082bfdb4f6b2823962f7f90ec5a7fe1fc78e3e7 Mon Sep 17 00:00:00 2001
From: Richard Earnshaw <rearnsha@arm.com>
Date: Mon, 13 Nov 2000 13:58:51 +0000
Subject: [PATCH] arm.md (mulsidi3adddi, [...]): Revert previous change.
* arm.md (mulsidi3adddi, umulsidi3adddi): Revert previous change.
Rewrite to avoid use of match_dup. Don't try to tie registers that
are not in the same mode.
From-SVN: r37425
---
gcc/ChangeLog | 6 ++++++
gcc/config/arm/arm.md | 20 ++++++++++----------
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 004b958145e7..bb2a1c5ab32d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2000-11-13 Richard Earnshaw <rearnsha@arm.com>
+
+ * arm.md (mulsidi3adddi, umulsidi3adddi): Revert previous change.
+ Rewrite to avoid use of match_dup. Don't try to tie registers that
+ are not in the same mode.
+
2000-11-13 Joseph S. Myers <jsm28@cam.ac.uk>
* invoke.texi: Update lists of languages and suffixes supported.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index a4d7b803321a..ddd6ace09337 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1263,14 +1263,14 @@
;; Unnamed template to match long long multiply-accumlate (smlal)
(define_insn "*mulsidi3adddi"
- [(set (match_operand:DI 0 "s_register_operand" "+&r,&r,&r")
+ [(set (match_operand:DI 0 "s_register_operand" "=&r")
(plus:DI
(mult:DI
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,0,1"))
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r,r,r")))
- (match_dup 0)))]
+ (sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
+ (sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
+ (match_operand:DI 1 "s_register_operand" "0")))]
"TARGET_ARM && arm_fast_multiply"
- "smlal%?\\t%Q0, %R0, %1, %2"
+ "smlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "type" "mult")
(set_attr "predicable" "yes")]
)
@@ -1300,14 +1300,14 @@
;; Unnamed template to match long long unsigned multiply-accumlate (umlal)
(define_insn "*umulsidi3adddi"
- [(set (match_operand:DI 0 "s_register_operand" "+&r,&r,&r")
+ [(set (match_operand:DI 0 "s_register_operand" "=&r")
(plus:DI
(mult:DI
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,0,1"))
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r,r,r")))
- (match_dup 0)))]
+ (zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
+ (zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
+ (match_operand:DI 1 "s_register_operand" "0")))]
"TARGET_ARM && arm_fast_multiply"
- "umlal%?\\t%Q0, %R0, %1, %2"
+ "umlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "type" "mult")
(set_attr "predicable" "yes")]
)
--
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