diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 652e88011c9fe0a33ead0086cf072f3424d67ec1..5dbfd1774be8a08fefbdcbbce71282d1c4b1efd4 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -15894,6 +15894,8 @@ ix86_build_const_vector (machine_mode mode, bool vect, rtx value)
case E_V2DImode:
gcc_assert (vect);
/* FALLTHRU */
+ case E_V2HFmode:
+ case E_V4HFmode:
case E_V8HFmode:
case E_V16HFmode:
case E_V32HFmode:
@@ -15935,6 +15937,8 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert)
switch (mode)
{
+ case E_V2HFmode:
+ case E_V4HFmode:
case E_V8HFmode:
case E_V16HFmode:
case E_V32HFmode:
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 6e6890c1458131a8d7b01e03d7019ca60f162ca4..c84a37a844434e4a56bb270b15cfeea489501d0c 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -99,7 +99,8 @@
;; Mapping of vector float modes to an integer mode of the same size
(define_mode_attr mmxintvecmode
- [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")])
+ [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")
+ (V4HF "V4HF") (V2HF "V2HI")])
(define_mode_attr mmxintvecmodelower
[(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi")])
@@ -2052,6 +2053,117 @@
DONE;
})
+(define_expand "<code><mode>2"
+ [(set (match_operand:VHF_32_64 0 "register_operand")
+ (absneg:VHF_32_64
+ (match_operand:VHF_32_64 1 "register_operand")))]
+ "TARGET_SSE"
+ "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
+
+(define_insn_and_split "*mmx_<code><mode>"
+ [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x,x")
+ (absneg:VHF_32_64
+ (match_operand:VHF_32_64 1 "register_operand" "0,x,x")))
+ (use (match_operand:VHF_32_64 2 "register_operand" "x,0,x"))]
+ "TARGET_SSE"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (<absneg_op>:<MODE> (match_dup 1) (match_dup 2)))]
+{
+ if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
+ std::swap (operands[1], operands[2]);
+}
+ [(set_attr "isa" "noavx,noavx,avx")])
+
+(define_insn_and_split "*mmx_nabs<mode>2"
+ [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x,x")
+ (neg:VHF_32_64
+ (abs:VHF_32_64
+ (match_operand:VHF_32_64 1 "register_operand" "0,x,x"))))
+ (use (match_operand:VHF_32_64 2 "register_operand" "x,0,x"))]
+ "TARGET_SSE"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (ior:<MODE> (match_dup 1) (match_dup 2)))])
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Parallel half-precision floating point logical operations
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define_insn "*mmx_andnot<mode>3"
+ [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x")
+ (and:VHF_32_64
+ (not:VHF_32_64
+ (match_operand:VHF_32_64 1 "register_operand" "0,x"))
+ (match_operand:VHF_32_64 2 "register_operand" "x,x")))]
+ "TARGET_SSE"
+ "@
+ andnps\t{%2, %0|%0, %2}
+ vandnps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "V4SF")])
+
+(define_insn "<code><mode>3"
+ [(set (match_operand:VHF_32_64 0 "register_operand" "=x,x")
+ (any_logic:VHF_32_64
+ (match_operand:VHF_32_64 1 "register_operand" "%0,x")
+ (match_operand:VHF_32_64 2 "register_operand" " x,x")))]
+ "TARGET_SSE"
+ "@
+ <logic>ps\t{%2, %0|%0, %2}
+ v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog,sselog")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "V4SF")])
+
+(define_expand "copysign<mode>3"
+ [(set (match_dup 4)
+ (and:VHF_32_64
+ (not:VHF_32_64 (match_dup 3))
+ (match_operand:VHF_32_64 1 "register_operand")))
+ (set (match_dup 5)
+ (and:VHF_32_64 (match_dup 3)
+ (match_operand:VHF_32_64 2 "register_operand")))
+ (set (match_operand:VHF_32_64 0 "register_operand")
+ (ior:VHF_32_64 (match_dup 4) (match_dup 5)))]
+ "TARGET_SSE"
+{
+ operands[3] = ix86_build_signbit_mask (<MODE>mode, true, false);
+
+ operands[4] = gen_reg_rtx (<MODE>mode);
+ operands[5] = gen_reg_rtx (<MODE>mode);
+})
+
+(define_expand "xorsign<mode>3"
+ [(set (match_dup 4)
+ (and:VHF_32_64 (match_dup 3)
+ (match_operand:VHF_32_64 2 "register_operand")))
+ (set (match_operand:VHF_32_64 0 "register_operand")
+ (xor:VHF_32_64 (match_dup 4)
+ (match_operand:VHF_32_64 1 "register_operand")))]
+ "TARGET_SSE"
+{
+ operands[3] = ix86_build_signbit_mask (<MODE>mode, true, false);
+
+ operands[4] = gen_reg_rtx (<MODE>mode);
+})
+
+(define_expand "signbit<mode>2"
+ [(set (match_operand:<mmxintvecmode> 0 "register_operand")
+ (lshiftrt:<mmxintvecmode>
+ (subreg:<mmxintvecmode>
+ (match_operand:VHF_32_64 1 "register_operand") 0)
+ (match_dup 2)))]
+ "TARGET_SSE2"
+ "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode)-1);")
+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Parallel integral arithmetic
diff --git a/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c b/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c
new file mode 100644
index 0000000000000000000000000000000000000000..48aed14d60419cf45b3d52e93f81dda471a73862
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c
@@ -0,0 +1,91 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O1 -mavx512fp16 -mavx512vl -ftree-vectorize -fdump-tree-slp-details -fdump-tree-optimized" } */
+
+extern void abort ();
+
+static void do_test (void);
+
+#define DO_TEST do_test
+#define AVX512FP16
+#include "avx512-check.h"
+
+#define N 16
+_Float16 a[N] = {-0.1f, -3.2f, -6.3f, -9.4f,
+ -12.5f, -15.6f, -18.7f, -21.8f,
+ 24.9f, 27.1f, 30.2f, 33.3f,
+ 36.4f, 39.5f, 42.6f, 45.7f};
+_Float16 b[N] = {-1.2f, 3.4f, -5.6f, 7.8f,
+ -9.0f, 1.0f, -2.0f, 3.0f,
+ -4.0f, -5.0f, 6.0f, 7.0f,
+ -8.0f, -9.0f, 10.0f, 11.0f};
+_Float16 r[N];
+
+void
+__attribute__((noipa,noinline,optimize("O2")))
+abs_32 (void)
+{
+ r[0] = __builtin_fabsf16 (b[0]);
+ r[1] = __builtin_fabsf16 (b[1]);
+}
+
+void
+__attribute__((noipa,noinline,optimize("O2")))
+abs_64 (void)
+{
+ r[0] = __builtin_fabsf16 (b[0]);
+ r[1] = __builtin_fabsf16 (b[1]);
+ r[2] = __builtin_fabsf16 (b[2]);
+ r[3] = __builtin_fabsf16 (b[3]);
+}
+
+void
+__attribute__((noipa,noinline,optimize("O2")))
+neg_32 (void)
+{
+ r[0] = -b[0];
+ r[1] = -b[1];
+}
+
+void
+__attribute__((noipa,noinline,optimize("O2")))
+neg_64 (void)
+{
+ r[0] = -b[0];
+ r[1] = -b[1];
+ r[2] = -b[2];
+ r[3] = -b[3];
+}
+
+static void
+__attribute__ ((noinline, noclone))
+do_test (void)
+{
+ abs_32 ();
+ /* check results: */
+ for (int i = 0; i != 2; i++)
+ if (r[i] != __builtin_fabsf16 (b[i]))
+ abort ();
+
+ abs_64 ();
+ /* check results: */
+ for (int i = 0; i != 4; i++)
+ if (r[i] != __builtin_fabsf16 (b[i]))
+ abort ();
+
+ neg_32 ();
+ /* check results: */
+ for (int i = 0; i != 2; i++)
+ if (r[i] != -b[i])
+ abort ();
+
+ neg_64 ();
+ /* check results: */
+ for (int i = 0; i != 4; i++)
+ if (r[i] != -b[i])
+ abort ();
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized using 8 byte vectors" 2 "slp2" } } */
+/* { dg-final { scan-tree-dump-times "vectorized using 4 byte vectors" 2 "slp2" } } */
+/* { dg-final { scan-tree-dump-times {(?n)ABS_EXPR <vect} 2 "optimized" { target { ! ia32 } } } } */
+/* { dg-final { scan-tree-dump-times {(?n)= -vect} 2 "optimized" { target { ! ia32 } } } } */
diff --git a/gcc/testsuite/gcc.target/i386/part-vect-copysignhf.c b/gcc/testsuite/gcc.target/i386/part-vect-copysignhf.c
new file mode 100644
index 0000000000000000000000000000000000000000..811617bc3ddcbbac268f7ac277df6a063880593f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/part-vect-copysignhf.c
@@ -0,0 +1,60 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O1 -mavx512fp16 -mavx512vl -ftree-vectorize -fdump-tree-slp-details -fdump-tree-optimized" } */
+
+extern void abort ();
+
+static void do_test (void);
+
+#define DO_TEST do_test
+#define AVX512FP16
+#include "avx512-check.h"
+
+#define N 16
+_Float16 a[N] = {-0.1f, -3.2f, -6.3f, -9.4f,
+ -12.5f, -15.6f, -18.7f, -21.8f,
+ 24.9f, 27.1f, 30.2f, 33.3f,
+ 36.4f, 39.5f, 42.6f, 45.7f};
+_Float16 b[N] = {-1.2f, 3.4f, -5.6f, 7.8f,
+ -9.0f, 1.0f, -2.0f, 3.0f,
+ -4.0f, -5.0f, 6.0f, 7.0f,
+ -8.0f, -9.0f, 10.0f, 11.0f};
+_Float16 r[N];
+
+void
+__attribute__((noipa,noinline,optimize("O2")))
+copysign_32 (void)
+{
+ r[0] = __builtin_copysignf16 (1.0f, b[0]);
+ r[1] = __builtin_copysignf16 (1.0f, b[1]);
+}
+
+void
+__attribute__((noipa,noinline,optimize("O2")))
+copysign_64 (void)
+{
+ r[0] = __builtin_copysignf16 (1.0f, b[0]);
+ r[1] = __builtin_copysignf16 (1.0f, b[1]);
+ r[2] = __builtin_copysignf16 (1.0f, b[2]);
+ r[3] = __builtin_copysignf16 (1.0f, b[3]);
+}
+
+static void
+__attribute__ ((noinline, noclone))
+do_test (void)
+{
+ copysign_32 ();
+ /* check results: */
+ for (int i = 0; i != 2; i++)
+ if (r[i] != __builtin_copysignf16 (1.0f, b[i]))
+ abort ();
+
+ copysign_64 ();
+ /* check results: */
+ for (int i = 0; i != 4; i++)
+ if (r[i] != __builtin_copysignf16 (1.0f, b[i]))
+ abort ();
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized using 8 byte vectors" 1 "slp2" } } */
+/* { dg-final { scan-tree-dump-times "vectorized using 4 byte vectors" 1 "slp2" } } */
+/* { dg-final { scan-tree-dump-times ".COPYSIGN" 2 "optimized" { target { ! ia32 } } } } */
diff --git a/gcc/testsuite/gcc.target/i386/part-vect-xorsignhf.c b/gcc/testsuite/gcc.target/i386/part-vect-xorsignhf.c
new file mode 100644
index 0000000000000000000000000000000000000000..a8ec60a088ad6d096c9a6eb63adc6988ebd1bb3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/part-vect-xorsignhf.c
@@ -0,0 +1,60 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O1 -mavx512fp16 -mavx512vl -ftree-vectorize -fdump-tree-slp-details -fdump-tree-optimized" } */
+
+extern void abort ();
+
+static void do_test (void);
+
+#define DO_TEST do_test
+#define AVX512FP16
+#include "avx512-check.h"
+
+#define N 16
+_Float16 a[N] = {-0.1f, -3.2f, -6.3f, -9.4f,
+ -12.5f, -15.6f, -18.7f, -21.8f,
+ 24.9f, 27.1f, 30.2f, 33.3f,
+ 36.4f, 39.5f, 42.6f, 45.7f};
+_Float16 b[N] = {-1.2f, 3.4f, -5.6f, 7.8f,
+ -9.0f, 1.0f, -2.0f, 3.0f,
+ -4.0f, -5.0f, 6.0f, 7.0f,
+ -8.0f, -9.0f, 10.0f, 11.0f};
+_Float16 r[N];
+
+void
+__attribute__((noipa,noinline,optimize("O2")))
+xorsign_32 (void)
+{
+ r[0] = a[0] * __builtin_copysignf16 (1.0f, b[0]);
+ r[1] = a[1] * __builtin_copysignf16 (1.0f, b[1]);
+}
+
+void
+__attribute__((noipa,noinline,optimize("O2")))
+xorsign_64 (void)
+{
+ r[0] = a[0] * __builtin_copysignf16 (1.0f, b[0]);
+ r[1] = a[1] * __builtin_copysignf16 (1.0f, b[1]);
+ r[2] = a[2] * __builtin_copysignf16 (1.0f, b[2]);
+ r[3] = a[3] * __builtin_copysignf16 (1.0f, b[3]);
+}
+
+static void
+__attribute__ ((noinline, noclone))
+do_test (void)
+{
+ xorsign_32 ();
+ /* check results: */
+ for (int i = 0; i != 2; i++)
+ if (r[i] != a[i] * __builtin_copysignf16 (1.0f, b[i]))
+ abort ();
+
+ xorsign_64 ();
+ /* check results: */
+ for (int i = 0; i != 4; i++)
+ if (r[i] != a[i] * __builtin_copysignf16 (1.0f, b[i]))
+ abort ();
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized using 8 byte vectors" 1 "slp2" } } */
+/* { dg-final { scan-tree-dump-times "vectorized using 4 byte vectors" 1 "slp2" } } */
+/* { dg-final { scan-tree-dump-times ".XORSIGN" 2 "optimized" { target { ! ia32 } } } } */