From b5568f074bbe4dcda0995e58cad7778b3c0ceebf Mon Sep 17 00:00:00 2001
From: David Edelsohn <edelsohn@gnu.org>
Date: Mon, 15 Aug 2005 17:58:58 +0000
Subject: [PATCH] rs6000.md (QHSI): New mode macro.
* config/rs6000/rs6000.md (QHSI): New mode macro.
(wd): Extend mode attr for QImode and HImode
(dbits): New mode attr.
(zero_extend<mode>di2): Convert to mode macro.
From-SVN: r103118
---
gcc/ChangeLog | 7 ++
gcc/config/rs6000/rs6000.md | 170 +++++-------------------------------
2 files changed, 28 insertions(+), 149 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d0a9379ddbd8..59c74826582f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2005-08-15 David Edelsohn <edelsohn@gnu.org>
+
+ * config/rs6000/rs6000.md (QHSI): New mode macro.
+ (wd): Extend mode attr for QImode and HImode
+ (dbits): New mode attr.
+ (zero_extend<mode>di2): Convert to mode macro.
+
2005-08-15 Steve Ellcey <sje@cup.hp.com>
PR target/21841
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c873c8f6513a..7fbe2e5b67d0 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -134,6 +134,9 @@
; Any supported integer mode that fits in one register.
(define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
+; extend modes for DImode
+(define_mode_macro QHSI [QI HI SI])
+
; SImode or DImode, even if DImode doesn't fit in GPRs.
(define_mode_macro SDI [SI DI])
@@ -149,42 +152,45 @@
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
-(define_mode_attr wd [(SI "w") (DI "d")])
+(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
+
+; DImode bits
+(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
-(define_expand "zero_extendqidi2"
+(define_expand "zero_extend<mode>di2"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
+ (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
"TARGET_POWERPC64"
"")
-(define_insn ""
+(define_insn "*zero_extend<mode>di2_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
+ (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
"TARGET_POWERPC64"
"@
- lbz%U1%X1 %0,%1
- rldicl %0,%1,0,56"
+ l<wd>z%U1%X1 %0,%1
+ rldicl %0,%1,0,<dbits>"
[(set_attr "type" "load,*")])
-(define_insn ""
+(define_insn "*zero_extend<mode>di2_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
+ (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:DI 2 "=r,r"))]
"TARGET_64BIT"
"@
- rldicl. %2,%1,0,56
+ rldicl. %2,%1,0,<dbits>
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
+ (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 2 ""))]
"TARGET_POWERPC64 && reload_completed"
@@ -195,22 +201,22 @@
(const_int 0)))]
"")
-(define_insn ""
+(define_insn "*zero_extend<mode>di2_internal3"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
+ (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(zero_extend:DI (match_dup 1)))]
"TARGET_64BIT"
"@
- rldicl. %0,%1,0,56
+ rldicl. %0,%1,0,<dbits>
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
- (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
+ (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(zero_extend:DI (match_dup 1)))]
@@ -280,73 +286,6 @@
(const_int 0)))]
"")
-(define_expand "zero_extendhidi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
- "TARGET_POWERPC64"
- "")
-
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
- "TARGET_POWERPC64"
- "@
- lhz%U1%X1 %0,%1
- rldicl %0,%1,0,48"
- [(set_attr "type" "load,*")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:DI 2 "=r,r"))]
- "TARGET_64BIT"
- "@
- rldicl. %2,%1,0,48
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 2 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 2)
- (zero_extend:DI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (match_dup 1)))]
- "TARGET_64BIT"
- "@
- rldicl. %0,%1,0,48
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
- (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (match_dup 1)))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 1)))
- (set (match_dup 2)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_expand "extendhidi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
@@ -414,73 +353,6 @@
(const_int 0)))]
"")
-(define_expand "zero_extendsidi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
- "TARGET_POWERPC64"
- "")
-
-(define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
- "TARGET_POWERPC64"
- "@
- lwz%U1%X1 %0,%1
- rldicl %0,%1,0,32"
- [(set_attr "type" "load,*")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:DI 2 "=r,r"))]
- "TARGET_64BIT"
- "@
- rldicl. %2,%1,0,32
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 2 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 2)
- (zero_extend:DI (match_dup 1)))
- (set (match_dup 0)
- (compare:CC (match_dup 2)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (match_dup 1)))]
- "TARGET_64BIT"
- "@
- rldicl. %0,%1,0,32
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
- (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (match_dup 1)))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (match_dup 1)))
- (set (match_dup 2)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_expand "extendsidi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
--
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