diff --git a/gcc/loop-iv.cc b/gcc/loop-iv.cc
index 0ac7e8bc39631d5a33e1c31b9a716363908f9af2..9165f18db4768dcb611dd299f911d956b8a2e6fe 100644
--- a/gcc/loop-iv.cc
+++ b/gcc/loop-iv.cc
@@ -714,6 +714,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
 	  if (!simple_reg_p (op0) || !CONSTANT_P (op1))
 	    return false;
 
+	  op1 = simplify_gen_unary (code, outer_mode, op1, GET_MODE (rhs));
 	  prev_code = code;
 	  code = PLUS;
 	}
diff --git a/gcc/testsuite/gcc.dg/pr117506.c b/gcc/testsuite/gcc.dg/pr117506.c
new file mode 100644
index 0000000000000000000000000000000000000000..4f25324645b8bdb30816b2dcf0756f6759e97726
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr117506.c
@@ -0,0 +1,18 @@
+/* PR rtl-optimization/117506 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -funroll-loops" } */
+
+char a;
+int b;
+unsigned c;
+short d;
+
+void
+foo ()
+{
+  for (short f = 0; f < c; f += 3)
+    {
+      a ^= d;
+      b = b < 0 ? b : 0;
+    }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/pr117506.c b/gcc/testsuite/gcc.target/riscv/pr117506.c
new file mode 100644
index 0000000000000000000000000000000000000000..ac4b9e35d63511e855a640a8735d85f62084b84d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr117506.c
@@ -0,0 +1,5 @@
+/* PR rtl-optimization/117506 */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64im_zve64f -mabi=lp64 -O3 -funroll-loops" } */
+
+#include "../../gcc.dg/pr117506.c"