From c5f673dbc252e35e6b66e9b8abd30a4027193e0b Mon Sep 17 00:00:00 2001
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Mon, 7 Aug 2023 09:54:31 +0800
Subject: [PATCH] tree-optimization/110897 - Fix missed vectorization of shift
 on both RISC-V and aarch64

Consider this following case:

#include <stdint.h>

#define TEST2_TYPE(TYPE)					\
  __attribute__((noipa))					\
  void vshiftr_##TYPE (TYPE *__restrict dst, TYPE *__restrict a, TYPE *__restrict b, int n)	\
  {								\
    for (int i = 0; i < n; i++)					\
      dst[i] = (a[i]) >> b[i];					\
  }

#define TEST_ALL()	\
 TEST2_TYPE(uint8_t)	\
 TEST2_TYPE(uint16_t)	\
 TEST2_TYPE(uint32_t)	\
 TEST2_TYPE(uint64_t)	\

TEST_ALL()

Both RISC-V and aarch64 of trunk GCC failed vectorize uint8_t/uint16_t with following missed report:

<source>:17:1: missed: couldn't vectorize loop
<source>:17:1: missed: not vectorized: relevant stmt not supported: patt_46 = MIN_EXPR <_6, 7>;
<source>:17:1: missed: couldn't vectorize loop
<source>:17:1: missed: not vectorized: relevant stmt not supported: patt_47 = MIN_EXPR <_7, 15>;
Compiler returned: 0

Both GCC 13.1 can vectorize, see:

https://godbolt.org/z/6vaMK5M1o

Bootstrap and regression on X86 passed.

Ok for trunk ?

gcc/ChangeLog:

	* tree-vect-patterns.cc (vect_recog_over_widening_pattern): Add op vectype.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Adapt testcase.
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c | 4 ++--
 gcc/tree-vect-patterns.cc                                   | 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c
index 3de8d85b52da..b12cb6355c8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c
@@ -27,5 +27,5 @@
 
 TEST_ALL ()
 
-/* { dg-final { scan-assembler-times {\tvnsra\.wv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvnsrl\.wv} 5 } } */
+/* { dg-final { scan-assembler-times {\tvnsra\.wv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvnsrl\.wv} 4 } } */
diff --git a/gcc/tree-vect-patterns.cc b/gcc/tree-vect-patterns.cc
index 2cedf2384505..cda27fed95bb 100644
--- a/gcc/tree-vect-patterns.cc
+++ b/gcc/tree-vect-patterns.cc
@@ -3133,7 +3133,8 @@ vect_recog_over_widening_pattern (vec_info *vinfo,
 		return NULL;
 	    }
 	  else
-	    append_pattern_def_seq (vinfo, last_stmt_info, pattern_stmt);
+	    append_pattern_def_seq (vinfo, last_stmt_info, pattern_stmt,
+				    op_vectype);
 	  ops[1] = new_var;
 	}
     }
-- 
GitLab