diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 327da33bc5f4d9180d9a4797b1b38e79083fffac..00d210211da33c796a266ef45cd794aa83f1caa2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,32 @@
+2002-01-15 Kazu Hirata <kazu@hxi.com>
+
+ * expmed.c (extract_fixed_bit_field): Remove unused code.
+ * system.h: Poison SLOW_ZERO_EXTEND.
+ * doc/tm.texi: Remove.
+ * config/1750a/1750a.h (SLOW_ZERO_EXTEND): Remove.
+ * config/arm/arm.h: Likewise.
+ * config/avr/avr.h: Likewise.
+ * config/clipper/clipper.h: Likewise.
+ * config/convex/convex.h: Likewise.
+ * config/d30v/d30v.h: Likewise.
+ * config/dsp16xx/dsp16xx.h: Likewise.
+ * config/elxsi/elxsi.h: Likewise.
+ * config/fr30/fr30.h: Likewise.
+ * config/h8300/h8300.h: Likewise.
+ * config/i370/i370.h: Likewise.
+ * config/i386/i386.h: Likewise.
+ * config/m68k/m68k.h: Likewise.
+ * config/mips/mips.h: Likewise.
+ * config/ns32k/ns32k.h: Likewise.
+ * config/pdp11/pdp11.h: Likewise.
+ * config/pj/pj.h: Likewise.
+ * config/s390/s390.h: Likewise.
+ * config/sh/sh.h: Likewise.
+ * config/stormy16/stormy16.h: Likewise.
+ * config/v850/v850.h: Likewise.
+ * config/vax/vax.h: Likewise.
+ * config/we32k/we32k.h: Likewise.
+
2002-01-15 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md (altivec_stvx): Add parallels to stvx.
diff --git a/gcc/config/1750a/1750a.h b/gcc/config/1750a/1750a.h
index 21d60e91a2b63f5ee22820d6b6f849f5c5f6c9f9..d93d81fddcb79d56dd1c1813480d2aa31c329c21 100644
--- a/gcc/config/1750a/1750a.h
+++ b/gcc/config/1750a/1750a.h
@@ -770,9 +770,6 @@ enum reg_class { NO_REGS, R2, R0_1, INDEX_REGS, BASE_REGS, ALL_REGS, LIM_REG_CLA
move-instruction pairs, we will do a movstr or libcall instead. */
#define MOVE_RATIO 4
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index ef07ceae8ab5ab4341afcbee902a73cb35af6bfc..5a7b9b543d344edcec9d72c286af3524f881a855 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2385,11 +2385,6 @@ typedef struct
((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
: ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
-/* Define this if zero-extension is slow (more than one real instruction).
- On the ARM, it is more than one instruction only if not fetching from
- memory. */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h
index efa47626331c3d57a1963766f950db95d06053d1..d3a33faec40fe01d67857a8630b26d224ea55f14 100644
--- a/gcc/config/avr/avr.h
+++ b/gcc/config/avr/avr.h
@@ -1797,18 +1797,6 @@ do { \
subsequent accesses occur to other fields in the same word of the
structure, but to different bytes.
- `SLOW_ZERO_EXTEND'
- Define this macro if zero-extension (of a `char' or `short' to an
- `int') can be done faster if the destination is a register that is
- known to be zero.
-
- If you define this macro, you must have instruction patterns that
- recognize RTL structures like this:
-
- (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
- and likewise for `HImode'.
-
`SLOW_UNALIGNED_ACCESS'
Define this macro to be the value 1 if unaligned accesses have a
cost many times greater than aligned accesses, for example if they
diff --git a/gcc/config/clipper/clipper.h b/gcc/config/clipper/clipper.h
index 473cab60ed1167cbecbc835c34c86bbc434b8f41..790202b4e36a6a0fd53150d1b539ee270ca33236 100644
--- a/gcc/config/clipper/clipper.h
+++ b/gcc/config/clipper/clipper.h
@@ -796,9 +796,6 @@ do \
#define MOVE_RATIO 20
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
diff --git a/gcc/config/convex/convex.h b/gcc/config/convex/convex.h
index 7f3d41c8833855345ffcfb1a26a5c99557b7301f..72224630c68a420ab29ed4b6e984c67092dd7f82 100644
--- a/gcc/config/convex/convex.h
+++ b/gcc/config/convex/convex.h
@@ -1031,9 +1031,6 @@ enum reg_class {
in one reasonably fast instruction. */
#define MOVE_MAX 8
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS (! TARGET_C2)
diff --git a/gcc/config/d30v/d30v.h b/gcc/config/d30v/d30v.h
index 6b9d3818560970b5c7e6e6d69fb7699e4658638a..a48934401f821f899dad8554c5c256281d167cd6 100644
--- a/gcc/config/d30v/d30v.h
+++ b/gcc/config/d30v/d30v.h
@@ -3432,17 +3432,6 @@ extern const char *d30v_branch_cost_string;
same word of the structure, but to different bytes. */
#define SLOW_BYTE_ACCESS 1
-/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
- be done faster if the destination is a register that is known to be zero.
-
- If you define this macro, you must have instruction patterns that recognize
- RTL structures like this:
-
- (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
- and likewise for `HImode'. */
-#define SLOW_ZERO_EXTEND 0
-
/* Define this macro to be the value 1 if unaligned accesses have a cost many
times greater than aligned accesses, for example if they are emulated in a
trap handler.
diff --git a/gcc/config/dsp16xx/dsp16xx.h b/gcc/config/dsp16xx/dsp16xx.h
index a2370cfb4ab54f1293429f0a818038bfe7c5a89e..ae2f72569a2996380fae504c35f1504859016915 100644
--- a/gcc/config/dsp16xx/dsp16xx.h
+++ b/gcc/config/dsp16xx/dsp16xx.h
@@ -1565,10 +1565,6 @@ extern struct dsp16xx_frame_info current_frame_info;
loads. */
#define SLOW_BYTE_ACCESS 1
-/* Define this macro if zero-extension (of a char or short to an int) can
- be done faster if the destination is a register that is know to be zero. */
-/* #define SLOW_ZERO_EXTEND */
-
/* Define this macro if unaligned accesses have a cost many times greater than
aligned accesses, for example if they are emulated in a trap handler */
/* define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) */
diff --git a/gcc/config/elxsi/elxsi.h b/gcc/config/elxsi/elxsi.h
index 6ff4d3cc83b3c4f82a5289b83eddeae541901c3c..d5969d4ea2b2eaa06d9eb9072ce054c0c94d255d 100644
--- a/gcc/config/elxsi/elxsi.h
+++ b/gcc/config/elxsi/elxsi.h
@@ -577,9 +577,6 @@ enum reg_class { NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
in one reasonably fast instruction. */
#define MOVE_MAX 8
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h
index 760ab22d941511b48e60634a4e7f87fc18fe933c..6bda37d33ede48b0bbe75ee184dd1b93abf77a98 100644
--- a/gcc/config/fr30/fr30.h
+++ b/gcc/config/fr30/fr30.h
@@ -1359,17 +1359,6 @@ do \
same word of the structure, but to different bytes. */
#define SLOW_BYTE_ACCESS 1
-/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
- be done faster if the destination is a register that is known to be zero.
-
- If you define this macro, you must have instruction patterns that recognize
- RTL structures like this:
-
- (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
- and likewise for `HImode'. */
-#define SLOW_ZERO_EXTEND 0
-
/*}}}*/
/*{{{ Dividing the output into sections. */
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index 3c782d482be357e3ded6d5647652962d9e46fdb6..d7d89b02c4250160945f77a848563896adf56e58 100644
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -965,9 +965,6 @@ struct cum_arg
#define MOVE_MAX (TARGET_H8300H || TARGET_H8300S ? 4 : 2)
#define MAX_MOVE_MAX 4
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS TARGET_SLOWBYTE
diff --git a/gcc/config/i370/i370.h b/gcc/config/i370/i370.h
index 7c71b0e2077762445d70060568257c436a745074..c2c7d4aeaa6d1facbe74fcfdb95900a9f6234ceb 100644
--- a/gcc/config/i370/i370.h
+++ b/gcc/config/i370/i370.h
@@ -874,10 +874,6 @@ enum reg_class
#define MOVE_MAX 256
-/* Define this if zero-extension is slow (more than one real instruction). */
-
-#define SLOW_ZERO_EXTEND 1
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 1
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 8f8e208d1a4aafe2b800a50d6972c5a37331c4e0..4f2b9038ded0603ed5ea182dd459b0225f581553 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2681,19 +2681,6 @@ do { \
/* Nonzero if access to memory by shorts is slow and undesirable. */
#define SLOW_SHORT_ACCESS 0
-/* Define this macro if zero-extension (of a `char' or `short' to an
- `int') can be done faster if the destination is a register that is
- known to be zero.
-
- If you define this macro, you must have instruction patterns that
- recognize RTL structures like this:
-
- (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
- and likewise for `HImode'. */
-
-/* #define SLOW_ZERO_EXTEND */
-
/* Define this macro to be the value 1 if unaligned accesses have a
cost many times greater than aligned accesses, for example if they
are emulated in a trap handler.
diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
index dc0835a230858bc9bf5a9ef1f98e566ea470e012..d97978c46e950d8ae279e9c911568487dffc8597 100644
--- a/gcc/config/m68k/m68k.h
+++ b/gcc/config/m68k/m68k.h
@@ -1529,9 +1529,6 @@ __transfer_from_trampoline () \
in one reasonably fast instruction. */
#define MOVE_MAX 4
-/* Define this if zero-extension is slow (more than one real instruction). */
-#define SLOW_ZERO_EXTEND
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index a6e572e04a8644a64b5ebab10640e6bac109eb54..2c3588a30e37218c84a3fe2ba6d60c3f092fe66b 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -3378,9 +3378,6 @@ while (0)
#define STORE_FLAG_VALUE 1
-/* Define this if zero-extension is slow (more than one real instruction). */
-#define SLOW_ZERO_EXTEND
-
/* Define this to be nonzero if shift instructions ignore all but the low-order
few bits. */
#define SHIFT_COUNT_TRUNCATED 1
diff --git a/gcc/config/ns32k/ns32k.h b/gcc/config/ns32k/ns32k.h
index 40dc12c34615e8c8d8e1410b17f9f1e5486f43f0..159148dbb31f9a067fc24070e9ac2cd43c80ec44 100644
--- a/gcc/config/ns32k/ns32k.h
+++ b/gcc/config/ns32k/ns32k.h
@@ -1116,9 +1116,6 @@ while (0)
We have a smart movstrsi insn */
#define MOVE_RATIO 0
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h
index 30bb630c2cb09860d00557fc927c518d50e4a90e..2c16aa80ddbb48f5dc50f31e6ceb7b647e44ed51 100644
--- a/gcc/config/pdp11/pdp11.h
+++ b/gcc/config/pdp11/pdp11.h
@@ -888,9 +888,6 @@ extern int may_call_alloca;
#define MOVE_MAX 2
-/* Zero extension is faster if the target is known to be zero */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by byte is slow and undesirable. -
*/
#define SLOW_BYTE_ACCESS 0
diff --git a/gcc/config/pj/pj.h b/gcc/config/pj/pj.h
index f56564df20747ff42eefe36ea79bf5e71d88e690..655ae0d64981c26c10e11be4f16a90eee05002a0 100644
--- a/gcc/config/pj/pj.h
+++ b/gcc/config/pj/pj.h
@@ -932,11 +932,6 @@ struct pj_args
#define SHORT_IMMEDIATES_SIGN_EXTEND
-/* Define this if zero-extension is slow (more than one real
- instruction). */
-
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is no faster than for words. */
#define SLOW_BYTE_ACCESS 1
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index b21f4daef80ef4642a0cf5c6c287d5fc1b689242..57e39aa5f86243b70d16b6fe71b964ad95d319fa 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -1061,10 +1061,6 @@ CUMULATIVE_ARGS;
#define MOVE_MAX 256
-/* Define this if zero-extension is slow (more than one real instruction). */
-
-#define SLOW_ZERO_EXTEND
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 1
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index b4b7e8ee0e969626acee504ad237fcdbe640b494..98939decb50b9294e923d93e93f16cbadf9704a7 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1682,10 +1682,6 @@ extern int current_function_anonymous_args;
/* Define if loading short immediate values into registers sign extends. */
#define SHORT_IMMEDIATES_SIGN_EXTEND
-/* Define this if zero-extension is slow (more than one real instruction).
- On the SH, it's only one instruction. */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is no faster than for words. */
#define SLOW_BYTE_ACCESS 1
diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h
index 4b125a751b70cd69f91c7a5539481c308043e61c..bffcdfc1208859f91d75b7d48b97553bd5ab5284 100644
--- a/gcc/config/stormy16/stormy16.h
+++ b/gcc/config/stormy16/stormy16.h
@@ -3193,17 +3193,6 @@ do { \
same word of the structure, but to different bytes. */
#define SLOW_BYTE_ACCESS 0
-/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
- be done faster if the destination is a register that is known to be zero.
-
- If you define this macro, you must have instruction patterns that recognize
- RTL structures like this:
-
- (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
- and likewise for `HImode'. */
-#define SLOW_ZERO_EXTEND 0
-
/* Define this macro to be the value 1 if unaligned accesses have a cost many
times greater than aligned accesses, for example if they are emulated in a
trap handler.
diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h
index 64bdc205c5777ba5318b8cd9aa469e8cebd0a768..7e0cdb63e800ecb6592eb38365c66c7e750d3323 100644
--- a/gcc/config/v850/v850.h
+++ b/gcc/config/v850/v850.h
@@ -1031,9 +1031,6 @@ do { \
than accessing full words. */
#define SLOW_BYTE_ACCESS 1
-/* Define this if zero-extension is slow (more than one real instruction). */
-#define SLOW_ZERO_EXTEND
-
/* According expr.c, a value of around 6 should minimize code size, and
for the V850 series, that's our primary concern. */
#define MOVE_RATIO 6
diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h
index 47a086650b925579155fa59f90ec18248853dc7d..26e767d37d0777b97138cb99780ccc6720b71d18 100644
--- a/gcc/config/vax/vax.h
+++ b/gcc/config/vax/vax.h
@@ -807,9 +807,6 @@ enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES };
in one reasonably fast instruction. */
#define MOVE_MAX 8
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
diff --git a/gcc/config/we32k/we32k.h b/gcc/config/we32k/we32k.h
index 98a29b4fad11161af16248dd40af962e8f6e55b7..12f105d8fae0bb65022ee9d29a136b7f6df1677a 100644
--- a/gcc/config/we32k/we32k.h
+++ b/gcc/config/we32k/we32k.h
@@ -599,9 +599,6 @@ enum reg_class { NO_REGS, GENERAL_REGS,
in one reasonably fast instruction. */
#define MOVE_MAX 4
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 360198a845da167005ab043bb95b9e53a20afcf8..c81461d1b5a858592c4f6bf606691052dc9cc347 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -5176,22 +5176,6 @@ faster than word accesses, using word accesses is preferable since it
may eliminate subsequent memory access if subsequent accesses occur to
other fields in the same word of the structure, but to different bytes.
-@findex SLOW_ZERO_EXTEND
-@item SLOW_ZERO_EXTEND
-Define this macro if zero-extension (of a @code{char} or @code{short}
-to an @code{int}) can be done faster if the destination is a register
-that is known to be zero.
-
-If you define this macro, you must have instruction patterns that
-recognize RTL structures like this:
-
-@smallexample
-(set (strict_low_part (subreg:QI (reg:SI @dots{}) 0)) @dots{})
-@end smallexample
-
-@noindent
-and likewise for @code{HImode}.
-
@findex SLOW_UNALIGNED_ACCESS
@item SLOW_UNALIGNED_ACCESS (@var{mode}, @var{alignment})
Define this macro to be the value 1 if memory accesses described by the
diff --git a/gcc/expmed.c b/gcc/expmed.c
index da9c5a9872b48e5dbb01e0498bf8acd4d1e28f97..56952c78418a8e717ee344b318bc4a37235dfacd 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -1621,16 +1621,7 @@ extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
/* Unless the msb of the field used to be the msb when we shifted,
mask out the upper bits. */
- if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
-#if 0
-#ifdef SLOW_ZERO_EXTEND
- /* Always generate an `and' if
- we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
- will combine fruitfully with the zero-extend. */
- || tmode != mode
-#endif
-#endif
- )
+ if (GET_MODE_BITSIZE (mode) != bitpos + bitsize)
return expand_binop (GET_MODE (op0), and_optab, op0,
mask_rtx (GET_MODE (op0), 0, bitsize, 0),
target, 1, OPTAB_LIB_WIDEN);
diff --git a/gcc/system.h b/gcc/system.h
index 1cbfe33bf1eafb8cd880c0f6276becc7d79117c5..08be6449bdd986e5f6099b0594dc3d87be71a1c8 100644
--- a/gcc/system.h
+++ b/gcc/system.h
@@ -604,7 +604,8 @@ typedef char _Bool;
DOESNT_NEED_UNWINDER EH_TABLE_LOOKUP OBJC_SELECTORS_WITHOUT_LABELS \
OMIT_EH_TABLE EASY_DIV_EXPR IMPLICIT_FIX_EXPR \
LONGJMP_RESTORE_FROM_STACK MAX_INT_TYPE_SIZE ASM_IDENTIFY_GCC \
- STDC_VALUE TRAMPOLINE_ALIGN ASM_IDENTIFY_GCC_AFTER_SOURCE
+ STDC_VALUE TRAMPOLINE_ALIGN ASM_IDENTIFY_GCC_AFTER_SOURCE \
+ SLOW_ZERO_EXTEND
#endif /* IN_GCC */