diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 8d3970b28db04d42780df2ca870ed52db98757b3..60c6e16f6aed4734618937582e0bda5c6274e323 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -424,6 +424,29 @@ public:
   }
 };
 
+/* Implements below instructions for frm
+   - vfnmsac
+*/
+class vfnmsac_frm : public function_base
+{
+public:
+  bool has_rounding_mode_operand_p () const override { return true; }
+
+  bool has_merge_operand_p () const override { return false; }
+
+  rtx expand (function_expander &e) const override
+  {
+    if (e.op_info->op == OP_TYPE_vf)
+      return e.use_ternop_insn (
+	true, code_for_pred_mul_neg_scalar (PLUS, e.vector_mode ()));
+    if (e.op_info->op == OP_TYPE_vv)
+      return e.use_ternop_insn (
+	true, code_for_pred_mul_neg (PLUS, e.vector_mode ()));
+
+    gcc_unreachable ();
+  }
+};
+
 /* Implements vrsub.  */
 class vrsub : public function_base
 {
@@ -2186,6 +2209,7 @@ static CONSTEXPR const widen_binop_frm<MULT> vfwmul_frm_obj;
 static CONSTEXPR const vfmacc vfmacc_obj;
 static CONSTEXPR const vfmacc_frm vfmacc_frm_obj;
 static CONSTEXPR const vfnmsac vfnmsac_obj;
+static CONSTEXPR const vfnmsac_frm vfnmsac_frm_obj;
 static CONSTEXPR const vfmadd vfmadd_obj;
 static CONSTEXPR const vfnmsub vfnmsub_obj;
 static CONSTEXPR const vfnmacc vfnmacc_obj;
@@ -2424,6 +2448,7 @@ BASE (vfwmul_frm)
 BASE (vfmacc)
 BASE (vfmacc_frm)
 BASE (vfnmsac)
+BASE (vfnmsac_frm)
 BASE (vfmadd)
 BASE (vfnmsub)
 BASE (vfnmacc)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index ca8a6dc1cc3ce837c24598f8c6a1f425c583b3cc..28eec2c3e997883fb12a151c47348901fe720097 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -162,6 +162,7 @@ extern const function_base *const vfwmul_frm;
 extern const function_base *const vfmacc;
 extern const function_base *const vfmacc_frm;
 extern const function_base *const vfnmsac;
+extern const function_base *const vfnmsac_frm;
 extern const function_base *const vfmadd;
 extern const function_base *const vfnmsub;
 extern const function_base *const vfnmacc;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 51a14e49075ce8a5e41dcb0d8a642cc8288088bb..c84e052c1a91d0b3e476e8b218019e49950a2871 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -355,6 +355,8 @@ DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops)
 DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
 DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvvv_ops)
 DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvvv_ops)
+DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvfv_ops)
 
 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
 DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c
new file mode 100644
index 0000000000000000000000000000000000000000..c308923427212420e4b0b2f7d2f7040f4e4095de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmsac_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+			        vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfnmsac_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+			    vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfnmsac_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfnmsac_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
+			  size_t vl) {
+  return __riscv_vfnmsac_vf_f32m1_rm (vd, op1, op2, 2, vl);
+}
+
+vfloat32m1_t
+test_vfnmsac_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
+			    vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfnmsac_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfnmsac_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1,
+			     vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfnmsac_vv_f32m1 (vd, op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfnmsac_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+			 vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfnmsac_vv_f32m1_m (mask, vd, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfnmsac\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */