From cdefeea2e6b4fc847fd23ff4d438b3c9db00d5a7 Mon Sep 17 00:00:00 2001
From: Will Schmidt <will_schmidt@vnet.ibm.com>
Date: Thu, 18 May 2017 14:08:13 +0000
Subject: [PATCH] fold-vec-div-float.c: Update dg-requires and dg-options
statements.
2017-05-18 Will Schmidt <will_schmidt@vnet.ibm.com>
[gcc/testsuite]
* fold-vec-div-float.c: Update dg-requires and dg-options statements.
* fold-vec-div-floatdouble.c: Likewise.
* fold-vec-logical-ands-char.c: Likewise.
* fold-vec-logical-ands-int.c: Likewise.
* fold-vec-logical-ands-short.c: Likewise.
* fold-vec-logical-ors-char.c: Likewise.
* fold-vec-logical-ors-int.c: Likewise.
* fold-vec-logical-ors-short.c: Likewise.
* fold-vec-logical-other-char.c: Likewise.
* fold-vec-mule-misc.c: Likewise.
* fold-vec-mult-float.c: Likewise.
* fold-vec-mult-floatdouble.c: Likewise.
* fold-vec-mult-int.c: Likewise.
* fold-vec-mult-int128-p9.c: Likewise.
* fold-vec-sub-floatdouble.c: Likewise.
* fold-vec-div-longlong.c: Update dg-requires and dg-options statements.
Add lp64 requirement.
* fold-vec-mult-int128-p8.c: Likewise.
* fold-vec-logical-ors-longlong.c: Fix comment typo.
From-SVN: r248202
---
gcc/testsuite/ChangeLog | 22 +++++++++++++++++++
.../gcc.target/powerpc/fold-vec-div-float.c | 6 ++---
.../powerpc/fold-vec-div-floatdouble.c | 4 ++--
.../powerpc/fold-vec-div-longlong.c | 5 +++--
.../powerpc/fold-vec-logical-ands-char.c | 2 +-
.../powerpc/fold-vec-logical-ands-int.c | 4 ++--
.../powerpc/fold-vec-logical-ands-short.c | 4 ++--
.../powerpc/fold-vec-logical-ors-char.c | 3 +--
.../powerpc/fold-vec-logical-ors-int.c | 4 ++--
.../powerpc/fold-vec-logical-ors-longlong.c | 2 +-
.../powerpc/fold-vec-logical-ors-short.c | 4 ++--
.../powerpc/fold-vec-logical-other-char.c | 2 +-
.../gcc.target/powerpc/fold-vec-mule-misc.c | 4 ++--
.../gcc.target/powerpc/fold-vec-mult-float.c | 4 ++--
.../powerpc/fold-vec-mult-floatdouble.c | 2 +-
.../gcc.target/powerpc/fold-vec-mult-int.c | 2 +-
.../powerpc/fold-vec-mult-int128-p8.c | 3 ++-
.../powerpc/fold-vec-mult-int128-p9.c | 2 +-
.../powerpc/fold-vec-sub-floatdouble.c | 2 +-
19 files changed, 52 insertions(+), 29 deletions(-)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 98c8081547d0..d20ade3afcd9 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,25 @@
+2017-05-18 Will Schmidt <will_schmidt@vnet.ibm.com>
+
+ * fold-vec-div-float.c: Update dg-requires and dg-options statements.
+ * fold-vec-div-floatdouble.c: Likewise.
+ * fold-vec-logical-ands-char.c: Likewise.
+ * fold-vec-logical-ands-int.c: Likewise.
+ * fold-vec-logical-ands-short.c: Likewise.
+ * fold-vec-logical-ors-char.c: Likewise.
+ * fold-vec-logical-ors-int.c: Likewise.
+ * fold-vec-logical-ors-short.c: Likewise.
+ * fold-vec-logical-other-char.c: Likewise.
+ * fold-vec-mule-misc.c: Likewise.
+ * fold-vec-mult-float.c: Likewise.
+ * fold-vec-mult-floatdouble.c: Likewise.
+ * fold-vec-mult-int.c: Likewise.
+ * fold-vec-mult-int128-p9.c: Likewise.
+ * fold-vec-sub-floatdouble.c: Likewise.
+ * fold-vec-div-longlong.c: Update dg-requires and dg-options statements.
+ Add lp64 requirement.
+ * fold-vec-mult-int128-p8.c: Likewise.
+ * fold-vec-logical-ors-longlong.c: Fix comment typo.
+
2017-05-18 Steven Munroe <munroesj@gcc.gnu.org>
* gcc.target/powerpc/bmi-andn-1.c: Fix-up dg-options.
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-float.c
index 8e8f645baf42..47254ce66a83 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-float.c
@@ -1,9 +1,9 @@
/* Verify that overloaded built-ins for vec_div with float
- inputs produce the right results with -maltivec. */
+ inputs produce the right results. */
/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-floatdouble.c
index 0559013dc332..569467e61f94 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-floatdouble.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-floatdouble.c
@@ -1,9 +1,9 @@
/* Verify that overloaded built-ins for vec_div with float and
- double inputs for VSX produce the right results with -mvsx. */
+ double inputs for VSX produce the right results. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-maltivec" } */
+/* { dg-options "-mvsx" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
index c37c64858176..312e984d3cc0 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
@@ -2,8 +2,9 @@
inputs produce the right results. */
/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-maltivec -mpower8-vector -O3" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mvsx -O2" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-char.c
index 021da58441e1..d1f66f434add 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-char.c
@@ -3,7 +3,7 @@
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-maltivec -O1" } */
+/* { dg-options "-mvsx -O1" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-int.c
index ccac7d5f8f23..59a23e89b485 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-int.c
@@ -2,8 +2,8 @@
* with int inputs produce the right results. */
/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O1" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O1" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-short.c
index 8ee320675b15..805d34561bad 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-short.c
@@ -2,8 +2,8 @@
inputs produce the right results. */
/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O1" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O1" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-char.c
index 283189f87134..7406039d0549 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-char.c
@@ -3,11 +3,10 @@
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-maltivec -O1" } */
+/* { dg-options "-mvsx -O1" } */
#include <altivec.h>
-
vector signed char
test1_or (vector bool char x, vector signed char y)
{
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-int.c
index 11e98ae4dcf9..a7c6366b938b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-int.c
@@ -2,8 +2,8 @@
* with int inputs produce the right results. */
/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O1" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O1" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c
index ac532f52d0c3..7ca23fb24543 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c
@@ -153,7 +153,7 @@ test6_nor (vector unsigned long long x, vector unsigned long long y)
// Codegen on power7 is such that the vec_or() tests generate more xxlor
// instructions than what is seen on power8 or newer.
-// Thus, an additional target close for the xxlor instruction check.
+// Thus, an additional target clause for the xxlor instruction check.
/* { dg-final { scan-assembler-times {\mxxlor\M} 6 { target p8vector_hw } } } */
/* { dg-final { scan-assembler-times {\mxxlor\M} 24 { target { ! p8vector_hw } } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-short.c
index 24f3a55efe01..8352a7f4dc59 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-short.c
@@ -2,8 +2,8 @@
inputs produce the right results. */
/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O1" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O1" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c
index 8726df617de4..7fe3e0b8e0e9 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c
@@ -3,7 +3,7 @@
* vec_nand) were added as part of ISA 2.07 (P8). */
/* { dg-do compile } */
-/* { dg-require-effective-target p8vector_hw } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-options "-mpower8-vector -O1" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
index 4bb618531693..9b89118a0fa7 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
@@ -1,8 +1,8 @@
/* PR target/79941 */
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mvsx -O2 -save-temps" } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -save-temps" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-float.c
index 619cd6eaed8b..46afc6855700 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-float.c
@@ -2,8 +2,8 @@
inputs produce the right results. */
/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-floatdouble.c
index 685318a322b8..59e936154e95 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-floatdouble.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-floatdouble.c
@@ -3,7 +3,7 @@
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-maltivec -mvsx" } */
+/* { dg-options "-mvsx" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c
index 3359fbec61c7..b536bcedaa9f 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c
@@ -3,7 +3,7 @@
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-maltivec -mvsx -mpower8-vector" } */
+/* { dg-options "-mpower8-vector" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c
index a133c5d90fe8..97d6b945f43e 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c
@@ -4,7 +4,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-require-effective-target int128 } */
-/* { dg-options "-maltivec -mvsx -mpower8-vector" } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mpower8-vector" } */
/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */
#include "altivec.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c
index 96c9d0196822..e81ea5f31343 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c
@@ -5,7 +5,7 @@
/* { dg-require-effective-target powerpc_float128_hw_ok } */
/* { dg-require-effective-target int128 } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-maltivec -mvsx -mcpu=power9 -O2" } */
+/* { dg-options "-mcpu=power9 -O2" } */
/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */
#include "altivec.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c
index c29acc93b564..116f15e66887 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c
@@ -3,7 +3,7 @@
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-maltivec -mvsx" } */
+/* { dg-options "-mvsx" } */
#include <altivec.h>
--
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