From d626200a86646ffd7997d5eb50f5754781a0e6bf Mon Sep 17 00:00:00 2001
From: Jeffrey A Law <law@cygnus.com>
Date: Tue, 9 Mar 1999 01:09:52 +0000
Subject: [PATCH] i386.md (zero_extendhisi2): Split into an expander and
anonymous pattern.
* i386.md (zero_extendhisi2): Split into an expander and anonymous
pattern. Add new anonymous pattern for use when optimizing for
size or for the PPro.
(zero_extendqihi2, zero_extendqisi2): Likewise.
From-SVN: r25650
---
gcc/ChangeLog | 7 ++++++
gcc/config/i386/i386.md | 52 ++++++++++++++++++++++++++++++++++++-----
2 files changed, 53 insertions(+), 6 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3a5dea4fcd58..b8cdfdfc1f6d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+Tue Mar 9 02:08:17 1999 Jeffrey A Law (law@cygnus.com)
+
+ * i386.md (zero_extendhisi2): Split into an expander and anonymous
+ pattern. Add new anonymous pattern for use when optimizing for
+ size or for the PPro.
+ (zero_extendqihi2, zero_extendqisi2): Likewise.
+
Mon Mar 8 23:43:47 1999 Richard Henderson <rth@cygnus.com>
* haifa-sched.c (sched_analyze_1): Fix last change -- add clobber
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 8ae917c1801b..8c3f4153dbc3 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1789,10 +1789,25 @@
;;- zero extension instructions
;; See comments by `andsi' for when andl is faster than movzx.
-(define_insn "zero_extendhisi2"
+(define_expand "zero_extendhisi2"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
+ ""
+ "")
+
+;; When optimizing for the PPro/PII or code size, always use movzwl.
+;; We want to use a different pattern so we can use different constraints
+;; than the generic pattern.
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
+ "(optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
+ "* return AS2 (movz%W0%L0,%1,%0);")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,&r,?r")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,rm,rm")))]
- ""
+ "! (optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
"*
{
rtx xops[2];
@@ -1853,10 +1868,23 @@
(const_int 65535)))]
"operands[2] = gen_rtx_REG (HImode, true_regnum (operands[0]));")
-(define_insn "zero_extendqihi2"
+(define_expand "zero_extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
+ "optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO"
+
+ "* return AS2 (movz%B0%W0,%1,%0);")
+
+(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=q,&q,?r")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm,qm")))]
- ""
+ "! (optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
"*
{
rtx xops[2];
@@ -1934,10 +1962,22 @@
FAIL;
operands[2] = gen_rtx_REG (HImode, REGNO (operands[1]));")
-(define_insn "zero_extendqisi2"
+(define_expand "zero_extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
+ "optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO"
+ "* return AS2 (movz%B0%L0,%1,%0);")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=q,&q,?r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm,qm")))]
- ""
+ "! (optimize_size || (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
"*
{
rtx xops[2];
--
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