From d7b6cad9d6c40f1dab907abd8e71e713bb2a5bf5 Mon Sep 17 00:00:00 2001
From: Patrick O'Neill <patrick@rivosinc.com>
Date: Wed, 16 Aug 2023 11:55:41 -0700
Subject: [PATCH] RISCV: Add rotate immediate regression test
This adds new regression tests to ensure half-register rotations are
correctly optimized into rori instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-rol-ror-08.c: New test.
* gcc.target/riscv/zbb-rol-ror-09.c: New test.
Co-authored-by: Charlie Jenkins <charlie@rivosinc.com>
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
.../gcc.target/riscv/zbb-rol-ror-08.c | 25 +++++++++++++++++++
.../gcc.target/riscv/zbb-rol-ror-09.c | 15 +++++++++++
2 files changed, 40 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
new file mode 100644
index 000000000000..30696f3bb32f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+/*
+**foo1:
+** rori a0,a0,32
+** ret
+*/
+unsigned long foo1(unsigned long rotate)
+{
+ return (rotate << 32) | (rotate >> 32);
+}
+
+/*
+**foo2:
+** roriw a0,a0,16
+** ret
+*/
+unsigned int foo2(unsigned int rotate)
+{
+ return (rotate << 16) | (rotate >> 16);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
new file mode 100644
index 000000000000..a3054553e184
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+/*
+**foo1:
+** rori a0,a0,16
+** ret
+*/
+unsigned int foo1(unsigned int rs1)
+{
+ return (rs1 << 16) | (rs1 >> 16);
+}
--
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