diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2667865e51cc8199424b96c2cd131ea21d6c8e97..aaeb52368d3f15e75f364cd9c2b749773014b0e1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,102 @@ +2023-05-02 Andrew Pinski <apinski@marvell.com> + + * tree-ssa-phiopt.cc (move_stmt): New function. + (match_simplify_replacement): Use move_stmt instead + of the inlined version. + +2023-05-02 Andrew Pinski <apinski@marvell.com> + + * match.pd (a != 0 ? CLRSB(a) : CST -> CLRSB(a)): New + pattern. + +2023-05-02 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/109702 + * match.pd: Fix "a != 0 ? FUNC(a) : CST" patterns + for FUNC of POPCOUNT BSWAP FFS PARITY CLZ and CTZ. + +2023-05-02 Andrew Pinski <apinski@marvell.com> + + PR target/109657 + * config/aarch64/aarch64.md (*cmov<mode>_insn_m1): New + insn_and_split pattern. + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + * config/riscv/sync.md (atomic_load<mode>): Implement atomic + load mapping. + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + * config/riscv/sync.md (mem_thread_fence_1): Change fence + depending on the given memory model. + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + * config/riscv/riscv-protos.h (riscv_union_memmodels): Expose + riscv_union_memmodels function to sync.md. + * config/riscv/riscv.cc (riscv_union_memmodels): Add function to + get the union of two memmodels in sync.md. + (riscv_print_operand): Add %I and %J flags that output the + optimal LR/SC flag bits for a given memory model. + * config/riscv/sync.md: Remove static .aqrl bits on LR op/.rl + bits on SC op and replace with optimized %I, %J flags. + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + * config/riscv/riscv.cc + (riscv_memmodel_needs_amo_release): Change function name. + (riscv_print_operand): Remove unneeded %F case. + * config/riscv/sync.md: Remove unneeded fences. + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + PR target/89835 + * config/riscv/sync.md (atomic_store<mode>): Use simple store + instruction in combination with fence(s). + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + * config/riscv/riscv.cc (riscv_print_operand): Change behavior + of %A to include release bits. + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + * config/riscv/sync.md (atomic_cas_value_strong<mode>): Change + FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl + pair. + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + * config/riscv/sync.md: Change LR.aq/SC.rl pairs into + sequentially consistent LR.aqrl/SC.rl pairs. + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + * config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and + sanitize memmodel input with memmodel_base. + +2023-05-02 Yanzhang Wang <yanzhang.wang@intel.com> + Pan Li <pan2.li@intel.com> + + PR target/109617 + * config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128. + +2023-05-02 Romain Naour <romain.naour@gmail.com> + + * config/riscv/genrvv-type-indexer.cc: Use log2 from the C header, without + the namespace. + +2023-05-02 Martin Liska <mliska@suse.cz> + + * doc/invoke.texi: Update documentation based on param.opt file. + +2023-05-02 Richard Biener <rguenther@suse.de> + + PR tree-optimization/109672 + * tree-vect-stmts.cc (vectorizable_operation): For plus, + minus and negate always check the vector mode is word mode. + 2023-05-01 Andrew Pinski <apinski@marvell.com> * tree-ssa-phiopt.cc: Update comment about diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index d4349ffd34f051bc5eb7d1284c9bb585600b3a9e..61f8aade98f0b88025076c869d15668ac88cc3b3 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20230502 +20230503 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index e07918af725d44a62069df140464be669ab4b36d..5d8ca6d8191b9806e9b09be60ecba3702c3ac0b8 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,28 @@ +2023-05-02 Jason Merrill <jason@redhat.com> + + * pt.cc (instantiate_class_template): Skip the RECORD_TYPE + of a class template. + (tsubst_template_decl): Clear CLASSTYPE_USE_TEMPLATE. + +2023-05-02 Jason Merrill <jason@redhat.com> + + * name-lookup.cc (pop_from_top_level): Don't + invalidate_class_lookup_cache. + +2023-05-02 Jason Merrill <jason@redhat.com> + + PR c++/109678 + * cp-tree.h (lookup_base): Add offset parm. + * constexpr.cc (cxx_fold_indirect_ref_1): Pass it. + * search.cc (struct lookup_base_data_s): Add offset. + (dfs_lookup_base): Handle it. + (lookup_base): Pass it. + +2023-05-02 Jason Merrill <jason@redhat.com> + + PR c++/109678 + * constexpr.cc (cxx_fold_indirect_ref_1): Handle empty base first. + 2023-05-01 Jason Merrill <jason@redhat.com> PR c++/109666 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6c3163b0418311ad3026c80de8edeab08e3a1279..3746564f18385c9c220b807f3c1c933460291fd7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,72 @@ +2023-05-02 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/109702 + * gcc.dg/tree-ssa/phi-opt-25b.c: New test. + +2023-05-02 Andrew Pinski <apinski@marvell.com> + + PR target/109657 + * gcc.target/aarch64/csinv-2.c: New test. + +2023-05-02 Jason Merrill <jason@redhat.com> + + PR c++/109678 + * g++.dg/cpp1z/variant1.C: New test. + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + * gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test. + * gcc.target/riscv/amo-table-a-6-amo-add-2.c: New test. + * gcc.target/riscv/amo-table-a-6-amo-add-3.c: New test. + * gcc.target/riscv/amo-table-a-6-amo-add-4.c: New test. + * gcc.target/riscv/amo-table-a-6-amo-add-5.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: New test. + * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: New test. + * gcc.target/riscv/amo-table-a-6-fence-1.c: New test. + * gcc.target/riscv/amo-table-a-6-fence-2.c: New test. + * gcc.target/riscv/amo-table-a-6-fence-3.c: New test. + * gcc.target/riscv/amo-table-a-6-fence-4.c: New test. + * gcc.target/riscv/amo-table-a-6-fence-5.c: New test. + * gcc.target/riscv/amo-table-a-6-load-1.c: New test. + * gcc.target/riscv/amo-table-a-6-load-2.c: New test. + * gcc.target/riscv/amo-table-a-6-load-3.c: New test. + * gcc.target/riscv/amo-table-a-6-store-1.c: New test. + * gcc.target/riscv/amo-table-a-6-store-2.c: New test. + * gcc.target/riscv/amo-table-a-6-store-compat-3.c: New test. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: New test. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: New test. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: New test. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: New test. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: New test. + +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + PR target/89835 + * gcc.target/riscv/pr89835.c: New test. + +2023-05-02 Yanzhang Wang <yanzhang.wang@intel.com> + Pan Li <pan2.li@intel.com> + + PR target/109617 + * gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test. + +2023-05-02 Patrick Palka <ppalka@redhat.com> + + PR c++/109506 + * g++.dg/cpp0x/nsdmi-template26.C: New test. + +2023-05-02 Richard Biener <rguenther@suse.de> + + * gcc.target/i386/pr88531-2a.c: Skip scanning for ia32. + * gcc.target/i386/pr88531-2b.c: Likewise. + * gcc.target/i386/pr88531-2c.c: Likewise. + * gcc.target/i386/pr89618-2.c: Likewise. Disable AVX512. + 2023-05-01 Jason Merrill <jason@redhat.com> PR c++/109666 diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 41556a7a79d03592c9912bc419d33ced88545800..1ebcf32a51abaa4ad5de02d6c42154830acd74d8 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,8 @@ +2023-05-02 Patrick O'Neill <patrick@rivosinc.com> + + * config/riscv/atomic.c: Change LR.aq/SC.rl pairs into + sequentially consistent LR.aqrl/SC.rl pairs. + 2023-05-01 Dimitar Dimitrov <dimitar@dinux.eu> * config/pru/t-pru (HOST_LIBGCC2_CFLAGS): Add diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index fb3f070f0a53f6d59d5287a6406d37a036575533..b52e22e9360584be8c9904154ade0142ecb3b382 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,20 @@ +2023-05-02 Jakub Jelinek <jakub@redhat.com> + + * config/abi/post/aarch64-linux-gnu/baseline_symbols.txt: Update. + * config/abi/post/i486-linux-gnu/baseline_symbols.txt: Update. + * config/abi/post/m68k-linux-gnu/baseline_symbols.txt: Update. + * config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt: Update. + * config/abi/post/riscv64-linux-gnu/baseline_symbols.txt: Update. + * config/abi/post/s390x-linux-gnu/baseline_symbols.txt: Update. + * config/abi/post/x86_64-linux-gnu/32/baseline_symbols.txt: Update. + * config/abi/post/x86_64-linux-gnu/baseline_symbols.txt: Update. + +2023-05-02 Jakub Jelinek <jakub@redhat.com> + + PR libstdc++/109694 + * src/c++98/ios_init.cc: Add #pragma GCC diagnostic ignored for + -Wattribute-alias. + 2023-04-28 Jonathan Wakely <jwakely@redhat.com> * include/bits/random.h (gamma_distribution): Add to the right