From e8511cbba692a9f3ff4d9c74e902fab03f154bbd Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng@sifive.com>
Date: Thu, 27 Apr 2023 22:00:39 +0800
Subject: [PATCH] Docs: Add vector register constarint for asm operands
`vr`, `vm` and `vd` constarint for vector register constarint, those 3
constarint has implemented on LLVM as well.
gcc/ChangeLog:
* doc/md.texi (RISC-V): Add vr, vm, vd constarint.
---
gcc/doc/md.texi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 07bf8bdebffb..cc4a93a87638 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3535,6 +3535,15 @@ An address that is held in a general-purpose register.
@item S
A constraint that matches an absolute symbolic address.
+@item vr
+A vector register (if available)..
+
+@item vd
+A vector register, excluding v0 (if available).
+
+@item vm
+A vector register, only v0 (if available).
+
@end table
@item RX---@file{config/rx/constraints.md}
--
GitLab